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PDF Z8L382 Data sheet ( Hoja de datos )
| Número de pieza | Z8L382 | |
| Descripción | HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS | |
| Fabricantes | Zilog | |
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PRELIMINARY PRODUCT SPECIFICATION
1
Z80382, Z8L382
HIGH-PERFORMANCE DATA
COMMUNICATIONS PROCESSORS
1
FEATURES
s Embedded Z380ª Microprocessor
Ð Maintains Object Code Compatibility with Z80¨
and Z180ª Microprocessors
Ð Enhanced Instruction Set for 16-Bit Operation
Ð 16 MB Linear Addressing
Ð Two Clock Cycle Instruction Execution Minimum
Ð Four On-Chip Register Banks
Ð BC/DE/HL/IX/IY Augmented to 32 Bits
Ð Clock Divide-by-Two and Multiply-by-Two Options
Ð Fully Static CMOS Design with Low-Power
Standby Mode
Ð 16-Bit Internal Bus
Ð Dynamic Bus Sizing (8/16-Bit Inter-Operability)
s 16550 Mimic with I/O Mailbox, DMA Mailbox, and 16 mA
Bus Drive
s Three HDLC Synchronous Serial Channels
Ð Serial Data Rate of up to 10 Mbps
s GCI/SCIT Bus Interface
s Eight Advanced DMA Channels with 24-Bit Addressing
s Plug-and-Play ISA Interface
s PCMCIA Interface
s Two Enhanced ASCIs (UARTs) with 16-Bit Baud Rate
Generators (BRG)
s Clocked Serial I/O Channel (CSIO) for Use with Serial
Memory
s Two 16-Bit Timers with Flexible Prescalers
s Three Memory Chip Selects with Wait-State Generators
s Watch-Dog Timer (WDT)
s Up to 32 General-Purpose I/O Pins
s DC to 20 MHz Operating Frequency @ 5.0V
s DC to 10 MHz Operating Frequency @ 3.3V
s 144-Pin QFP and VQFP Style Packages
GENERAL DESCRIPTION
The Z80382 (Z382) is designed to address high-end data
communication applications such as digital modems (IS-
DN, GSM, Mobitex & Modacom), xDSL and analog mo-
dems (V.34 and beyond). The Z382 provides a perfor-
mance upgrade to existing Z80- and Z18x-based designs
by utilizing the increased bandwidth of the 380C proces-
sor. The Z8L382 is a low voltage version of the device.
Note: In this document the notation Ò380CÓ denotes the
Z380-compatible CPU core which is embedded in the
Z382.
The 380C microprocessor is a high-performance proces-
sor with fast and efficient throughput and increased mem-
ory addressing capabilities. The 380C offers a continuing
growth path for present Z80- or Z18x-based designs, while
maintaining Z80 and Z180 object code compatibility. Its en-
hancements include added instructions, expanded16 MB
address space and flexible bus interface timing.
In the 380C, the basic addressing modes of the Z80 micro-
processor have been augmented to include Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing. Inter-
nally, all of the addressing modes allow up to 32-bit linear
addressing; however, because the Z382 has only 24 ad-
dress pins, it can only address 16 MB of memory.
DS97Z382000
PRELIMINARY
1
1 page  
Zilog
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VIN
TOPR
TSTG
Description
Supply Voltage
Input Voltage
Operating Temp
Storage Temp
Value
-0.3 to +7.0
-0.3 to VDD+0.3
0 to +70
-55 to +150
Unit
V
V
°C
°C
Z80382/Z8L382
High-Performance Data Communications Processors
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for extended periods
may affect device reliability.
1
STANDARD TEST CONDITIONS
The DC Characteristics which follow apply for the following
standard test conditions, unless otherwise noted. All volt-
ages are referenced to GND (0V). Positive current flows
into the referenced pin (Figure 3, Test Load Diagram).
s Operating temperature range:
Ð Standard: 0°C to 70°C
s Voltage Supply Range:
Ð +4.5V £ VDD £ +5.5V (Z80382 versions)
Ð +3.0V £ VDD £ +3.6V (Z8L382 versions)
All AC parameters assume a load capacitance of 50 pF.
Add 10 ns delay for each 50 pF increase in load up to a
maximum of 150 pF for the data bus and 100 pF for ad-
dress and control lines. AC timing measurements are ref-
erenced to 1.5 volts (except for clock, which is referenced
to the 10% and 90% points). Maximum capacitive load for
PHI is 125 pF.
IOL = 2 mA
100 pF
1.4V
IOH = 250 mA
Figure 3. Test Load Diagram
DS97Z382000
PRELIMINARY
5
5 Page 
Zilog
CLK
t5
BUSCLK
OUTPUT
OUTPUT
INPUT
t10, t14
INPUT
INPUT
INPUT
t3
t6
Z80382/Z8L382
High-Performance Data Communications Processors
t1
t2
1
t4
t7
t8
t11, t15
t9
t12, t16
t18, t19
t13, t17
t21
t20
Figure 4. 380C Processor Timing
DS97Z382000
PRELIMINARY
11
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| PDF Descargar | [ Datasheet Z8L382.PDF ] | |
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