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PDF SY58610U Data sheet ( Hoja de datos )
| Número de pieza | SY58610U | |
| Descripción | LVPECL 2:1 MUX | |
| Fabricantes | Micrel Semiconductor | |
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SY58610U
3.2Gbps Precision, LVPECL 2:1 MUX with
Internal Termination and Fail Safe Input
General Description
The SY58610U is a 2.5/3.3V, high-speed, fully
differential LVPECL 2:1 MUX capable of processing
clock signals up to 2.5GHz and data patterns up to
3.2Gbps. The SY58610U is optimized to provide a
buffered output of the selected input with less than
10pspp total jitter.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
reference voltage (VREF-AC) is provided to bias the VT pin.
The outputs are 800mV LVPECL, with extremely fast
rise/fall times guaranteed to be less than 130ps.
The SY58610U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require CML or LVDS outputs, consider
Micrel’s SY58609U and SY58611U, 2:1 MUX with
400mV and 325mV output swings, respectively. The
SY58610U is part of Micrel’s high-speed, Precision
Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Features
Precision Edge®
• Precision 800mV LVPECL 2:1 MUX
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <370ps propagation delay (IN-to-Q)
– <130ps rise/fall times
• Fail Safe Input
– Prevents outputs from oscillating when input is
invalid
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
• High-speed LVPECL outputs
• 2.5V ±5% or 3.3V ±10% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Applications
• All SONET clock distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
• Backplane distribution.
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 2006
M9999-111406-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58610U
AC Electrical Characteristics(8)
VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V; Input tR/tF < 300ps, TA = –40°C to +85°C, unless otherwise
stated.
Symbol
fMAX
tPD
tSkew
tJitter
tR, tF
Parameter
Maximum Frequency
Propagation Delay
IN-to-Q
SEL-to-Q
Input-to-Input Skew
Part-to-Part Skew
Data
Random Jitter
Deterministic Jitter
Clock
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Condition
NRZ Data
VOUT > 400mV
VIN: 100mV-200mV
VIN: >200mV
Note 9, 10
Note 11
Note 12
Note 13
Note 14
Note 15
At full output swing.
Differential I/O
Min Typ Max Units
3.2 Gbps
Clock 2.5
3
GHz
180 340 470 ps
140 290 370 ps
150 450 ps
5 20 ps
150 ps
1 psRMS
10 psPP
1 psRMS
10 psPP
40 100 130 ps
47 53 %
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9 Input-to-input skew is the time difference between the two inputs to one output, under identical input transitions.
10 Input-to-Input Skew is included in IN-to-Q propagation delay.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at
the edges at the respective inputs.
12. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10^12 output edges will deviate by
more than the specified peak-to-peak jitter value.
November 2006
5 M9999-111406-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input and Output Stage
SY58610U
Single-Ended and Differential Swings
Figure 3a. Single-Ended Voltage Swing
Figure 2a. Simplified Differential Input Buffer
Figure 3b. Differential Voltage Swing
Figure 2b. Simplified LVPECL Output Buffer
November 2006
11 M9999-111406-A
[email protected] or (408) 955-1690
11 Page | ||
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| PDF Descargar | [ Datasheet SY58610U.PDF ] | |
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