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54ACTQ373 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer 54ACTQ373
Beschreibung Quiet Series Octal Transparent Latch
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
54ACTQ373 Datasheet, Funktion
www.DataSheet4U.com
September 1998
54ACQ373 54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE®
Outputs
General Description
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT373
n 4 kV minimum ESD immunity (’ACQ)
n Standard Military Drawing (SMD)
— ’ACTQ373: 5962-92188
— ’ACQ373: 5962-92178
Logic Symbols
IEEE/IEC
DS100238-1
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
DS100238-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100238
www.national.com






54ACTQ373 Datasheet, Funktion
AC Operating Requirements
Symbol
Parameter
VCC
(V)
(Note 14)
ts Setup Time, HIGH or LOW
Dn to LE
th Hold Time, HIGH or LOW
Dn to LE
tw LE Pulse Width, HIGH
Note 14: Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH
Propagation Delay
Dn to On
tPHL, tPLH
Propagation Delay
LE to On
tPZL, tPZH
Output Enable Time
tPHZ, tPLZ
Output Disable Time
Note 15: Voltage Range 5.0 is 5.0V ±0.5V.
AC Operating Requirements
VCC
(V)
(Note 15)
5.0
5.0
5.0
5.0
Symbol
Parameter
VCC
(V)
(Note 16)
ts Setup Time, HIGH or LOW
Dn to LE
th Hold Time, HIGH or LOW
Dn to LE
tw LE Pulse Width, HIGH
Note 16: Voltage Range 5.0 is 5.0V ±0.5V
5.0
5.0
5.0
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ Units
4.5 pF
44.0 pF
54ACQ
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed Minimum
3.0
3.0
1.5
1,5
5.0
5.0
54ACTQ
TA = −55˚C
to +125˚C
CL = 50 pF
Min Max
1.5 10.5
1.5 11.5
1.5 11.0
1.5 10.5
54ACTQ
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed Minimum
3.5
1.5
5.0
Conditions
VCC = OPEN
VCC = 5.0V
Units
ns
ns
ns
Units
ns
ns
ns
ns
Units
ns
ns
ns
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