|
|
PDF 54AC109 Data sheet ( Hoja de datos )
| Número de pieza | 54AC109 | |
| Descripción | Dual JK Positive Edge-Triggered Flip-Flop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 54AC109 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
August 1998
54AC109 • 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n ICC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
DS100267-2
DS100267-7
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100267
www.national.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fmax Maximum Clock
Frequency
tPLH Propagation Delay
CPn to Qn or Qn
tPHL Propagation Delay
CPn to Qn or Qn
tPLH Propagation Delay
CDn or SDn to Qn or Qn
tPHL Propagation Delay
CDn or SDn to Qn or Qn
Note 8: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
Symbol
Parameter
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
VCC
(V)
(Note 9)
ts Setup Time, HIGH or LOW
Jn or Kn to CPn
th Hold Time, HIGH or LOW
Jn or Kn to CPn
tw Pulse Width
CDn or SDn or CPn
trec Recovery Time
CDn or SDn to CPn
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
54AC
TA = −55˚C
to +125˚C
CL = 50 pF
Min Max
65
95
1.0 17.5
1.0 12.0
1.0 13.5
1.0 10.0
1.0 13.0
1.0 9.5
1.0 14.0
1.0 10.5
Units
MHz
ns
ns
ns
ns
54AC
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed
Minimum
8.0
5.5
0
0.5
8.0
5.5
0.5
0.5
Units
ns
ns
ns
ns
Fig.
No.
Fig.
No.
5 www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 54AC109.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 54AC10 | Triple 3-Input NAND Gate | National Semiconductor |
| 54AC10 | 54AC10 Triple 3-Input NAND Gate |  Texas Instruments |
| 54AC109 | Dual JK Positive Edge-Triggered Flip-Flop | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |