PDF ZL30116 Data sheet ( Hoja de datos )

Número de pieza	ZL30116
Descripción	SONET/SDH Low Jitter System Synchronizer
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ZL30116 SONET/SDH Low Jitter System Synchronizer Data Sheet A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Features • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks • Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 1 ps RMS suitable for OC-48/STM-16 interfaces • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz • Provides two DPLLs which are independently configurable through a serial software interface • DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range • DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other general purpose clocks December 2005 Ordering Information ZL30116GGG 100 Pin CABGA Trays ZL30116GGG2 100 Pin CABGA* Trays Pb Free Tin/Silver/Copper -40oC to +85oC • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • Supports master/slave configuration for AdvancedTCATM • Configurable input to output delay and output to output phase alignment • Optional external feedback path provides dynamic input to output delay compensation • Provides 3 sync inputs for output frame pulse alignment • Generates several styles of output frame pulses with selectable pulse width, polarity and frequency • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Supports IEEE 1149.1 JTAG Boundary Scan osco osci ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 int_b trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en Master Clock IEEE 1449.1 JTAG ref7:0 sync2:0 Reference ref_&_sync_status Monitors DPLL2 ref ref DPLL1 sync fb_clk fb_fp P0 Synthesizer P1 Synthesizer SONET/SDH APLL Feedback Synthesizer p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 diff0 diff1 sdh_clk0 sdh_clk1 sdh_fp0 sdh_fp1 fb_clk SPI Interface sck si so cs_b Controller & State Machine rst_b slave_en dpll1_mod_sel1:0 ext_fb_clk ext_fb_fp sdh_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. 1 page www.DataSheet4U.com ZL30116 Data Sheet List of Tables Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Zarlink Semiconductor Inc. 5 Page www.DataSheet4U.com ZL30116 Data Sheet 1.0 Functional Description The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. 1.1 DPLL Features The ZL30116 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. Table 1 shows a feature summary for both DPLLs. Feature Modes of Operation Loop Bandwidth Phase Slope Limiting Pull-in Range Holdover Parameters Holdover Frequency Accuracy Reference Inputs Sync Inputs Input Ref Frequencies Supported Sync Input Frequencies Input Reference Selection/Switching Hitless Ref Switching Output Clocks Output Frame Pulses Supported Output Clock Frequencies DPLL1 DPLL2 Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover User selectable: 0.1 Hz, 1.7 Hz, 3.5 Hz, fast lock (7 Hz), or wideband1 (890 Hz / 56 Hz / 14 Hz) Fixed: 14 Hz User selectable: 885 ns/s, 7.5 µs/s, 61 µs/s, or unlimited User selectable: 12 ppm, 52 ppm, 83 ppm, 130 ppm User selectable: 61 µs/s, or unlimited Fixed: 130 ppm Selectable Update Times: 26 ms, 1 s, 10 s, 60 s, and Selectable Holdover Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz. Fixed Update Time: 26 ms No Holdover Post Filtering Better than 1 ppb (Stratum 3E) initial frequency offset. Frequency drift depends on the 20 MHz external oscillator. Better than 50 ppb (Stratum 3) initial frequency offset. Frequency drift depends on the 20 MHz external oscillator. Ref0 to Ref7 Ref0 to Ref7 Sync0, Sync1, Sync2 Sync inputs are not supported. 2 kHz, N 8 kHz up to 77.76 MHz 2 kHz, N * 8 kHz up to 77.76 MHz 166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz. Sync inputs are not supported. Automatic (based on programmable priority and revertiveness), or manual Automatic (based on programmable priority and revertiveness), or manual Can be enabled or disabled Can be enabled or disabled diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk. p0_clk0, p0_clk1, p1_clk0, p1_clk1. sdh_fp0, sdh_fp1, p0_fp0, p0_fp1 p0_fp0, p0_fp1 not synchronized to sync synchronized to active sync reference. reference. As listed in Table 4 As listed in Table 4 for p0_clk0, p0_clk1, p1_clk0, p1_clk1 Table 1 - DPLL1 and DPLL2 Features 11 Zarlink Semiconductor Inc. 11 Page

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