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PDF LMX2485E Data sheet ( Hoja de datos )
| Número de pieza | LMX2485E | |
| Descripción | High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 2006
LMX2485/LMX2485E
50 MHz - 3.0 GHz High Performance Delta-Sigma Low
Power Dual PLLatinum™ Frequency Synthesizers with
800 MHz Integer PLL
General Description
The LMX2485 is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. The device
is fabricated using National Semiconductor’s advanced pro-
cess.
With delta-sigma architecture, fractional spurs at lower offset
frequencies are pushed to higher frequencies outside the
loop bandwidth. The ability to push close in spur and phase
noise energy to higher frequencies is a direct function of the
modulator order. Unlike analog compensation, the digital
feedback technique used in the LMX2485 is highly resistant
to changes in temperature and variations in wafer process-
ing. The LMX2485 delta-sigma modulator is programmable
up to fourth order, which allows the designer to select the
optimum modulator order to fit the phase noise, spur, and
lock time requirements of the system.
Serial data for programming the LMX2485 is transferred via
a three line high speed (20 MHz) MICROWIRE interface.
The LMX2485 offers fine frequency resolution, low spurs,
fast programming speed, and a single word write to change
the frequency. This makes it ideal for direct digital modula-
tion applications, where the N counter is directly modulated
with information. The LMX2485 is available in a 24 lead
4.0 X 4.0 X 0.8 mm LLP package.
Applications
n Cellular phones and base stations
CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC
n Direct digital modulation applications
n Satellite and cable TV tuners
n WLAN Standards
Features
Quadruple Modulus Prescalers for Lower Divide Ratios
n RF PLL: 8/9/12/13 or 16/17/20/21
n IF PLL: 8/9 or 16/17
Advanced Delta Sigma Fractional Compensation
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
Features for Improved Lock Times and Programming
n Fastlock / Cycle slip reduction
n Integrated time-out counter
n Single word write to change frequencies with Fastlock
Wide Operating Range
n LMX2485 RF PLL: 500 MHz to 3.0 GHz
n LMX2485E RF PLL: 50 MHz to 3.0 GHz
Useful Features
n Digital lock detect output
n Hardware and software power-down control
n On-chip crystal reference frequency doubler.
n RF phase comparison frequency up to 50 MHz
n 2.5 to 3.6 volt operation with ICC = 5.0 mA at 3.0 V
Functional Block Diagram
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS200877
20087701
www.national.com
1 page  
Electrical Characteristics (VCC = 3.0V; -40˚C ≤ TA ≤ +85˚C unless otherwise specified) (Continued)
Symbol
Parameter
Conditions
PHASE NOISE
RF_CPG = 0
RF Synthesizer
RF_CPG = 1
LF1HzRF
Normalized Phase Noise RF_CPG = 3
Contribution (Note 7) RF_CPG = 7
RF_CPG = 15
IF Synthesizer
LF1HzIF
Normalized Phase Noise
Contribution
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
IIH High-Level Input Current VIH = VCC
IIL Low-Level Input Current VIL = 0 V
High-Level Output
VOH
Voltage
IOH = -500 µA
Low-Level Output
VOL Voltage
IOL = 500 µA
MICROWIRE INTERFACE TIMING
Data to Clock Set Up
tCS Time
See MICROWIRE Input Timing
tCH
tCWH
tCWL
tES
Data to Clock Hold Time See MICROWIRE Input Timing
Clock Pulse Width High See MICROWIRE Input Timing
Clock Pulse Width Low See MICROWIRE Input Timing
Clock to Load Enable
Set Up Time
See MICROWIRE Input Timing
Load Enable Pulse
tEW Width
See MICROWIRE Input Timing
Value
Min Typ
Max
Units
-202
-202
-206
-208
-210
dBc/Hz
-209
dBc/Hz
1.6
-1.0
-1.0
VCC-0.4
VCC
0.4
V
V
1.0 µA
1.0 µA
V
0.4 V
25 ns
8 ns
25 ns
25 ns
25 ns
25 ns
Note 3: A slew rate of at least 100 V/uS is recommended for frequencies below 500 MHz for optimal performance.
Note 4: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 5: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
Note 6: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset
frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the
impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency =
20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 7: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for
RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0.
MICROWIRE INPUT TIMING DIAGRAM
20087775
5 www.national.com
5 Page 
Typical Performance Characteristic : FinIF Input Impedance (Note 8)
Frequency (MHz)
50
75
100
200
300
400
500
600
700
800
900
1000
FinIF Input Impedance
Real (Ohms)
583
530
499
426
384
347
310
276
244
216
192
173
20087754
Imaginary (Ohms)
-286
-256
-241
-209
-209
-219
-224
-228
-228
-223
-218
-208
11 www.national.com
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet LMX2485E.PDF ] | |
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