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PDF CY7C924ADX Data sheet ( Hoja de datos )
| Número de pieza | CY7C924ADX | |
| Descripción | 200-MBaud HOTLink Transceiver | |
| Fabricantes | Cypress Semiconductor | |
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CY7C924ADX
200-MBaud HOTLink® Transceiver
Features
• Second-generation HOTLink® technology
• Fibre Channel and ESCON®-compliant 8B/10B
encoder/decoder
• 10- or 12-bit pre-encoded data path (raw mode)
• 8- or 10-bit encoded data transport (using 8B/10B
coding)
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
• Embedded/Bypassable 256-character synchronous
FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs
• Dual differential PECL-compatible serial outputs
• Compatible with fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
• Single +5.0V ±10% supply
• 100-pin TQFP
• 0.35µ CMOS technology
Functional Description
The 200-MBaud CY7C924ADX HOTLink Transceiver is a
point-to-point communications building block allowing the
transfer of data over high-speed serial links (optical fiber,
balanced, and unbalanced copper transmission lines) at
speeds ranging between 50 and 200 MBaud. The transmit
section accepts parallel data of selectable width and converts
it to serial data, while the receiver section accepts serial data
and converts it to parallel data of selectable width. Figure1
illustrates typical connections between two independent host
systems and corresponding CY7C924ADX parts. As a second
generation HOTLink device, the CY7C924ADX provides
enhanced levels of technology, functionality, and integration
over the field-proven CY7B923/933 HOTLink.
The transmit section of the CY7C924ADX HOTLink can be
configured to accept either 8- or 10-bit data characters on
each clock cycle, and stores the parallel data into an internal
Transmit FIFO. Data is read from the Transmit FIFO and is
encoded using an embedded 8B/10B encoder to improve its
serial transmission characteristics. These encoded characters
are then serialized and output from two Positive ECL (PECL)
compatible differential transmission line drivers at a bit-rate of
10 or 12 times the character rate.
The receive section of the CY7C924ADX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are
reconstructed into either 8- or 10-bit data characters, written
to an internal Receive FIFO, and presented to the destination
host system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface. The embedded FIFOs may also be
bypassed to create a reference-locked serial transmission link.
For those systems requiring even greater FIFO storage
capability, external FIFOs may be directly coupled to the
CY7C924ADX device through the parallel interface without
additional glue-logic.
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth
expansion through external FIFOs) or as a pipeline register
extender. The FIFO configurations are optimized for transport
of time-independent (asynchronous) 8- or 10-bit character-
oriented data across a link. A Built-In Self-Test (BIST) pattern
generator and checker permits at-speed testing of the high-
speed serial data paths in both the transmit and receive
sections, and across the interconnecting links.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Data
Receive
Control
Status
Data
Transmit
CY7C924ADX
Serial Link
Serial Link
CY7C924ADX
Transmit
Data
Control
Status
Receive
Data
Figure 1.HOTLink System Connections
CypressSemiconductorCorporation • 3901NorthFirstStreet • SanJose, CA 95134 • 408-943-2600
Document #: 38-02008 Rev. *D
Revised February 13, 2004
1 page  
CY7C924ADX
Pin Descriptions (continued)
CY7C924ADX HOTLink Transceiver
Pin #
Name
18 TXEN*
9 TXSTOP*
68 TXCLK
72 TXFULL*
70 TXHALF*
I/O Characteristics
Signal Description
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
Transmit Enable Input. Data enable for the TXDATA[11:0] data bus write
operations. Active HIGH when configured for Cascade timing (EXTFIFO is
HIGH), active LOW when configured for UTOPIA timing (EXTFIFO is LOW).
When the Transmit FIFO is enabled (FIFOBYP* is HIGH) and TXEN* is
asserted, data is loaded into the FIFO on every rising edge of TXCLK. When
TXEN* is deasserted with TXHALT* and TXSTOP* deasserted, data continues
to be read out of the Transmit FIFO and sent serially until the FIFO empties.
At this time, C5.0 (K28.5) idle characters are transmitted.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW) and TXEN* is
asserted, the parallel data on the TXDATA bus is clocked in and transmitted
on every appropriate REFCLK rising edge. When TXEN* is deasserted, the
parallel data bus is ignored and C5.0 sync characters are transmitted instead.
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
Transmit Stop on Start_Of_Cell Input. While the Transmit FIFO and Encoder
are enabled (FIFOBYP* and ENCBYP* are HIGH), this signal is used to
prevent queued data characters from being serially transmitted. While
TXSTOP* is deasserted, data flows through the Transmit FIFO without inter-
ruption. When TXSTOP* is asserted, data transfers continue until a TXSOC
bit is detected in the character stream, at which point data transmission ceases.
When transmission is stopped, C5.0 (K28.5) characters are sent instead.
If data transmission is suspended due to a SOC character, pulsing TXSTOP*
deasserted then asserted will allow only the next cell (delimited by SOC bits)
to be transmitted.
When the Transmit FIFO is bypassed (FIFOBYP* = LOW) TXSTOP* has no
function.
When the Transmit FIFO is enabled (FIFOBYP* is HIGH) and the Encoder is
bypassed (ENCBYP* is LOW), TXDATA[9]/TXHALT* is a data input and not
TXHALT*. In this mode, the TXSOC bit is not interpreted and the TXSTOP*
input assumes the same operation as TXHALT*. When soon as TXSTOP* is
asserted, data reads from the Transmit FIFO are suspended and alternating
disparity10-bit equivalents of C5.0 are transmitted instead.
TTL clock input,
Internal Pull-Up
Transmit FIFO Clock. The input clock for the parallel interface when the
Transmit FIFO is enabled (FIFOBYP* is HIGH). Used to sample all Transmit
FIFO related interface signals.
3-state TTL output,
changes following
TXCLK↑ or
REFCLK↑
Transmit FIFO Full Status Flag. Active HIGH when configured for Cascade
timing (EXTFIFO is HIGH), active LOW when configured for UTOPIA timing
(EXTFIFO is LOW). The TXFULL* output is enabled when AM* is asserted,
otherwise it is High-Z.
When the Transmit FIFO is enabled (FIFOBYP* is HIGH), TXFULL* Indicates
a Transmit FIFO full condition. When TXFULL* is first asserted, the Transmit
FIFO can accept up to eight additional write cycles without loss of data.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW), with RANGESEL
HIGH or SPDSEL LOW, TXFULL* toggles at half the REFCLK rate to provide
a character rate indication.
3-state TTL output,
changes following
TXCLK↑ or
REFCLK↑
Transmit FIFO Half-full Status Flag. The TXHALF* flag is always active
LOW, regardless of the EXTFIFO* setting.
When the Transmit FIFO is enabled, TXHALF* is asserted LOW when the
Transmit FIFO is ≥ half full (128 characters).
TXHALF* is only set to High-Z state by the assertion of RESET*[1:0] LOW.
Document #: 38-02008 Rev. *D
Page 5 of 56
5 Page 
CY7C924ADX
Pin Descriptions (continued)
CY7C924ADX HOTLink Transceiver
Pin #
Name
100 CARDET
3 LFI*
Power
80, 87, VDDA
88, 95,
96, 98
76, 79,
83, 84,
91, 92,
99
VSSA
14, 17, VDD
35, 55,
62, 64
11, 13,
15, 26,
37, 38,
39, 57,
63, 66
VS S
I/O Characteristics
Signal Description
PECL-compatible
input, asynchronous
Carrier Detect Input. Used to allow an external device to signify a valid signal
is being presented to the high speed PECL-compatible input buffers, as is
typical on an Optical Module. When CARDET is deasserted LOW, the LFI*
indicator asserts LOW signifying a Link Fault. This input can be tied to VDD for
copper media applications.
TTL output, changes Link Fault Indication Output. Active LOW. LFI* changes synchronous with
following RXCLK↑ RXCLK. This output is driven LOW when the serial link currently selected by
A/B* is not suitable for data recovery. This can be caused by
Serial Data Amplitude is below acceptable levels.
Input transition density is not sufficient for PLL clock recovery.
Serial Data stream is outside an acceptable frequency range of operation.
CARDET is LOW.
Power for PECL-compatible I/O signals and internal analog circuits.
Ground for PECL-compatible I/O signals and internal analog circuits.
Power for CMOS I/O signals and internal logic circuits.
Ground for CMOS I/O signals and internal logic circuits.
CY7C924ADX HOTLink Operation
Overview
The CY7C924ADX is designed to move parallel data across
both short and long distances with minimal overhead or host
system intervention. This is accomplished by converting the
parallel characters into a serial bit-stream, transmitting these
serial bits at high speed, and converting the received serial bits
back into the original parallel data format.
The CY7C924ADX offers a large feature set, allowing it to be
used in a wide range of host systems. Some of the configu-
ration options are:
• 8-bit, 10-bit or 12-bit character size
• user definable data packet or frame structure
• 2-octave data rate range
• asynchronous (FIFOed) or synchronous data interface
• 8B/10B encoded or non-encoded (raw data)
• embedded or bypassable FIFO data storage
• multi-PHY capability
• point-to-point, point-to-multipoint, or ring data-transport.
This flexibility allows the CY7C924ADX to meet the data-
transport needs of almost any system.
Transmit Data Path
Transmit Data Interface/Transmit Data FIFO
The transmit data interface to the host system is configurable
as either an asynchronous buffered (FIFOed) parallel interface
or as a synchronous pipeline register. The bus itself can be
configured for operation with 8-bit, 10-bit or 12-bit data.
When configured for asynchronous operation (where the host-
bus interface clock operates asynchronous to the serial
character and bit stream clocks), the host interface becomes
that of a synchronous FIFO clocked by TXCLK. In these
configurations an internal 256-character Transmit FIFO is
enabled. It allows the host interface to be written at any rate
from DC to 50MHz.
When configured for synchronous operation, the transmit
interface is clocked by REFCLK and operates synchronous to
the internal character and bit-stream clocks. The input register
must be written at the character rate, but REFCLK can operate
at the one, two or four times the character rate.
Both asynchronous and synchronous interface operations
support two interface timing models: UTOPIA and Cascade.
The UTOPIA timing model is designed to match the active
levels, bus timing, and signal sequencing called out in the ATM
Forum UTOPIA specification. The Cascade timing model is
designed to match a host bus that resembles a synchronous
FIFO. These timing models allow the CY7C924ADX to directly
Document #: 38-02008 Rev. *D
Page 11 of 56
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