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ZL30414 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL30414
Beschreibung SONET/SDH Clock Multiplier PLL
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 24 Seiten
ZL30414 Datasheet, Funktion
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ZL30414
SONET/SDH Clock Multiplier PLL
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-192, OC-48, OC-12, and OC-3
rates
• Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at
622.08 MHz
• Provides a CML differential clock at 155.52 MHz
• Provides a single-ended CMOS clock at 19.44
MHz
• Lock Indicator
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply
Applications
• SONET/SDH line cards
• Network Element timing cards
Data Sheet
February 2005
Ordering Information
ZL30414QGC 64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
-40°C to +85°C
Description
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
C19i
C622oEN-A
C622oEN-B
LPF C622oEN-C
C622oEN-D
Frequency
& Phase
Detector
Loop
Filter
State
Machine
Reference
and
Bias Circuit
LOCK
BIAS
VCO
19.44MHz
Frequency
Dividers
and
Clock
Drivers
C622oP/N-A
C622oP/N-B
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
VDD GND VCC
C155oEN
C19oEN
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
05






ZL30414 Datasheet, Funktion
ZL30414
Data Sheet
1.4 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
1.5 Output Interface Circuit
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at
622.08 MHz, one CML differential clock at 155.52 MHz and a single-ended 19.44 MHz output clock. This block
provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled
individually with the associated Output Enable pin.
Output Clocks
Output Enable Pins
C622oP/N-A
C622oEN-A
C622oP/N-B
C622oEN-B
C622oP/N-C
C622oEN-C
C622oP/N-D
C622oEN-D
C155oP/N
C155oEN
C19o
C19oEN
Table 1 - Output Enable Control
To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be
disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
6
Zarlink Semiconductor Inc.

6 Page









ZL30414 pdf, datenblatt
ZL30414
Data Sheet
3.2.3 CML to LVDS Interface
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage)
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
+3.3 V
ZL30414 VCC
CML
Driver
155.52 MHz
C155oP
C155oN
GND
0.1 uF
VCC=+3.3 V
Z=50
10 nF
R1 R1
Z=50
10 nF
R2 R2
LVDS
Receiver
100
Typical resistor values: R1 = 16 kΩ, R2 = 10 k
Figure 10 - LVDS Termination
3.2.4 CML to LVPECL Interface
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as
close as possible to the LVPECL receiver.
+3.3 V
ZL30414
CML
Driver
155.52 MHz
GND
VCC
C155oP
C155oN
0.1 uF
Z=50
Z=50
VCC=+3.3 V
10 nF R1 R1
10 nF
R2 R2
Typical resistor values: R1 = 82 , R2 =130
Figure 11 - CML to LVPECL Interface
LVPECL
Receiver
12
Zarlink Semiconductor Inc.

12 Page





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