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WM8152 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8152
Beschreibung Single Channel 16-bit CIS/CCD AFE
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 26 Seiten
WM8152 Datasheet, Funktion
www.DataSheet4U.com
WM8152
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
The WM8152 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes a complete analogue signal processing
channel containing Reset Level Clamping, Correlated
Double Sampling, Programmable Gain and Offset adjust
functions. Internal multiplexers allow fast switching of offset
and gain for line-by-line colour processing. The output from
this channel is time multiplexed into a high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used to reference CIS signals or
during Reset Level Clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V, a digital core
voltage of 5V, and a digital interface supply of either 5V or
3.3V, the WM8152 typically only consumes 225mW when
operating from a single 5V supply.
BLOCK DIAGRAM
FEATURES
16-bit ADC
12MSPS conversion rate
Low power - 225mW typical
5V single supply or 5V/3.3V dual supply operation
Single channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
20-pin SSOP package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
VSMP MCLK
AVDD DVDD1 DVDD2
VRT VRX VRB
CL RS VS TIMING CONTROL
VREF/BIAS
VINP
VRLC/VBIAS
RLC
CDS
RLC 4
DAC
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
RM
GU
X
8
OFFSET
DAC
B
RM
GU
X
B
+ PGA
I/P SIGNAL
8 POLARITY
ADJUST
+
W
WM8152
16-
BIT
ADC
DATA
I/O
PORT
OP[0]
OP[1]
OP[2]
OP[3]/SDO
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
SEN
SCK
SDI
AGND1
AGND2
DGND
Production Data, January 2004, Rev 4.0
Copyright 2004 Wolfson Microelectronics plc






WM8152 Datasheet, Funktion
WM8152
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP MAX
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.30
3.22
Input signal limits (see Note 2)
VIN
0 VDD
Full-scale transition error
Gain = 0dB;
-50 10 +50
PGA[7:0] = 07(hex)
Zero-scale transition error
Gain = 0dB;
-50 10 +50
PGA[7:0] = 07(hex)
Differential non-linearity
DNL
1.25
Integral non-linearity
INL
25
Total output noise
Min Gain
4.5
Max Gain
14
References
Upper reference voltage
VRT
2.70
Lower reference voltage
VRB
1.45
Input return bias voltage
VRX
1.55 1.65 1.75
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.15 1.25 1.35
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
20 50 100
VRLC short-circuit current
1.86 2 4.5
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD = 5.0V
AVDD = 5.0V
0.23
0.14
0.34
0.25 0.27
0.16 0.20
0.39 0.44
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.20 0.26 0.31
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
AVDD = 5.0V
4.0 4.16 4.3
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.56 2.66 2.76
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
0.1 0.5
Integral non-linearity
INL
0.25 1
Step size
2.04
Output voltage
Code 00(hex)
Code FF(hex)
-247
+247
-260
+260
-273
+273
Notes:
1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input
range.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
UNIT
Vp-p
Vp-p
V
mV
mV
LSB
LSB
LSB rms
LSB rms
V
V
V
V
mA
µA
bits
V/step
V/step
V
V
V
V
bits
LSB
LSB
mV/step
mV
mV
w
PD Rev 4.0 January 2004
6

6 Page









WM8152 pdf, datenblatt
WM8152
Production Data
MCLK
VSMP
VS
RS/CL (CDSREF = 00)
RS/CL (CDSREF = 01)
RS/CL (CDSREF = 10)
RS/CL (CDSREF = 11)
Figure 6 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this
mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set
for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or
B).
In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset
DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1.
INTM[1:0]
DESCRIPTION
00 Red offset and gain registers are applied to offset DAC and PGA
(DACR[7:0] and PGAR[7:0])
01 Green offset and gain registers applied to offset DAC and PGA
(DACG[7:0] and PGAG[7:0])
10 Blue offset and gain registers applied to offset DAC and PGA
(DACB[7:0] and PGAB[7:0])
11 Reserved.
Table 1 Offset DAC and PGA Register Control
The gain characteristic of the WM8152 PGA is shown in Figure 7. Figure 8 shows the maximum
input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.5V).
9
8
7
6
5
4
3
2
1
0
0 64 128 192 256
GAIN REGISTER VALUE, PGA[7:0]
3.5
3
2.5
2
1.5
1
0.5
0
0
64 128 192
GAIN REGISTER VALUE, PGA[7:0]
256
Figure 7 PGA Gain Characteristic
Figure 8 Peak Input Voltage to Match ADC Full-scale Range
w
PD Rev 4.0 January 2004
12

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