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U63764 Schematic ( PDF Datasheet ) - Simteh

Teilenummer U63764
Beschreibung CapStore 8K x 8 nvSRAM
Hersteller Simteh
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Gesamt 14 Seiten
U63764 Datasheet, Funktion
www.DataSheet4U.com
Obsolete - Not Recommended for New Designs
U63764
CapStore 8K x 8 nvSRAM
Features
Description
CMOS non- volatile static RAM The U63764 has two separate
8192 x 8 bits
modes of operation: SRAM mode
70 ns Access Time
and nonvolatile mode. In SRAM
35 ns Output Enable Access Time mode, the memory operates as an
ICC = 15 mA at 200 ns Cycle Time
Unlimited Read and Write Cycles
ordinary static RAM. In non-volatile
operation, data is transferred in
to SRAM
Automatic STORE to EEPROM
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using charge
mode SRAM functions are disab-
stored in an integrated capacitor
Software initiated STORE
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
led.
The U63764 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
EEPROM
Single 5 V ± 10 % Operation
Operating temperature range:
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
0 to 70 °C
using charge stored in an integra-
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
(MIL STD 883C M3015.7)
RoHS compliance and Pb- free
Package: PDIP28 (600 mil)
automatically on power up. The
U63764 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63764 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 PDIP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0055
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0






U63764 Datasheet, Funktion
U63764
Write Cycle #1: W-controlledj
Ai
E
W
DQi
Input
DQi
Output
tcW (12)
Address Valid
tsu(E) (17)
th(A) (21)
tsu(A)
(15)
tsu(A-WH) (16)
tw(W) (13)
tsu(D) (19)
th(D) (20)
Input Data Valid
tdis(W) (22)
ten(W) (23)
Previous Data
High Impedance
Write Cycle #2: E-controlledj
Ai
E
W
DQi
Input
DQi
Output
tsu(A) (15)
tcW (12)
Address Valid
tw(E) (18)
th(A) (21)
tsu(W) (14)
tsu(D) (19)
th(D) (20)
Input Data Valid
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
STK Control #ML0055
6
Rev 1.0
March 31, 2006

6 Page









U63764 pdf, datenblatt
U63764
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation. When VCC < VSWITCH all software STORE
operations will be inhibited.
Any SRAM WRITE cycles requested after the VCC pin
drops below VSWITCH will be inhibited.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read addresses 0000 (hex) Valid READ
2. Read addresses 1555 (hex) Valid READ
3. Read addresses 0AAA (hex) Valid READ
4. Read addresses 1FFF (hex) Valid READ
5. Read addresses 10F0 (hex) Valid READ
6. Read addresses 0F0E (hex) Initiate RECALL
Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
td(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
Low Average Active Power
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
STK Control #ML0055 12
Rev 1.0
March 31, 2006

12 Page





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