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LC78622NE Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC78622NE
Beschreibung Compact Disc Player DSP
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 30 Seiten
LC78622NE Datasheet, Funktion
www.DataSheet4U.com
Ordering number : EN6015
CMOS IC
LC78622NE
Compact Disc Player DSP
Overview
The LC78622NE is a CMOS IC that implements the
signal processing and servo control required by compact
disc players. At the same time as providing an EFM PLL
circuit, a 1-bit D/A converter, and an analog low-pass
filter the LC78622NE realizes an optimal cost-
performance tradeoff for low-end players by strictly
limiting functionality to basic signal-processing and servo
system functionality. The LC78622NE signal-processing
system provides demodulation of the EFM signal from the
pickup, de-interleaving, error detection and correction, and
digital filters that can prove useful in reducing the cost of
end products. The LC78622NE servo control system
processes servo commands sent from the control
microprocessor.
The LC78622NE is an improved version of the LC78622E
that adds 8× oversampling digital filters, three general-
purpose output ports (that also have specific shared
functions) and the PCCL pin (pin 34). However, some
handling of general-purpose ports differ from that of the
LC78622E, therefore care must be taken.(Refer to pages
16 and 21).
Functions
• Input signal processing: The LC78622NE takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output to a microprocessor over the
serial I/O interface after performing a CRC error check
(LSB first)
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• Sets the C2 flags based on the C1 flags and a C2 check,
and then performs signal interpolation or muting
depending on the C2 flags. The interpolation circuit uses
a dual-interpolation scheme. The previous value is held
if the C2 flags indicate errors two or more times
consecutively.
• Support for command input from a control
microprocessor: commands include track jump, focus
start, disk motor start/stop, muting on/off and track
count (8 bit serial input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• D/A converter outputs with data continuity improved by
8× oversampling digital filters.
• Built-in third-order ∑∆ D/A converters (An analog low-
pass filter is built in.)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
11999RM (OT) No. 6015-1/31






LC78622NE Datasheet, Funktion
LC78622NE
Figure 2 Subcode Q Output
Figure 3 Subcode Output
Figure 4 General-Purpose Port Input Timing
Figure 5 General-Purpose Port Output Timing
No. 6015-6/31

6 Page









LC78622NE pdf, datenblatt
LC78622NE
• CLV three-value output
MSB
LSB
10110100
10110101
Command
CLV THREE VALUE OUTPUT
CLV TWO VALUE OUTPUT
(the scheme used by previous products)
The CLV three-value output command allows the CLV to be controlled by a single pin.
RES = low
q
• Internal brake modes
MSB
LSB
11000101
11000100
10100011
11001011
11001010
11001101
11001100
Command
INTERNAL BRAKE ON
INTERNAL BRAKE OFF
INTERNAL BRAKE CONTROL
INTERNAL BRAKE CONTINUOUS MODE
RESET CONTINUOUS MODE
TON MODE DURING INTERNAL BRAKING
RESET TON MODE
RES = low
q
q
q
— Issuing the internal brake-on (C5H) command sets the LC78622NE to internal brake mode. In this mode, the
disk deceleration state can be monitored from the WRQ pin when a brake command (06H) is executed.
— In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and
when the EFM signal count falls under four, the CLVpin is dropped to low. At the same time the WRQ signal,
which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the
WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode (CBH),
the CLVpin high-level output braking operation continues even after the WRQ brake completion monitor
goes high.
Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem may be
rectified by changing the EFM signal count from four to eight with the internal brake control command (A3H).
— In TOFF output disabled mode (CDH), the TOFF pin is held low during internal brake operations. We
recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface.
No. 6015-12/31

12 Page





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