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KL5KUSB101 Schematic ( PDF Datasheet ) - Kawasaki

Teilenummer KL5KUSB101
Beschreibung USB to Ethernet Controller
Hersteller Kawasaki
Logo Kawasaki Logo 




Gesamt 17 Seiten
KL5KUSB101 Datasheet, Funktion
www.DataSheet4U.com
KL5KUSB101
General Description
USB to Ethernet Controller
The Kawasaki KL5KUSB101 Controller is a unique single chip solution to interface peripheral
devices to the Universal Serial Bus (USB) and Ethernet. The KL5KUSB101 has been specifically
designed to provide a simple solution to communicate with Ethernet applications as well as other
USB peripheral devices. This has been accomplished by its highly integrated functionality. The
USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator,
Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and
SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification.
This USB to Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area
Network), Cable Modem, Set Top Boxes, or Mobile Networking applications.
Features
Advanced 16 Bit processor for USB transaction
processing and control data processing
USB interface ver. 1.0/1.1 compliant
Transceivers and SIE (Serial Interface Engine)
Internal Clock Generation
Utilizes low cost external crystal circuitry
1.5K x 16 Internal RAM buffer
Serial Interface for external EEPROM
Block Diagram
Watchdog timer
Fully IEEE 802.3 compliant 10 Mbit/sec
Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.
UART
External memory interface
100 pin QFP and LQFP package
Txd
Rxd UART
CK EEPROM
Serial Interface
DIO
2
INT 1-0
IRQ
8 10Mb/s
Ethernet
Interface
Timer 0
Timer 1
RAM
(3KB)
Mask ROM
(8KB)
16 Bit
Processor
Watchdog
Timer
SRAM Interface
16 Bit Address / Data Bus
Serial
Interface
Engine
Clock
Generator
USB Interface
Data -
Data +
A15-0
D15-0
Cntrl .
X1
X2
Ver. 2.4
Kawasaki LSI 2570 North First Street Suite 301 San Jose, CA 95131 Tel: (408) 570-0555 Fax: (408) 570-0567 www.klsi.com
1






KL5KUSB101 Datasheet, Funktion
KL5KUSB101
USB to Ethernet Controller
Function Description
16 Bit Processor
The integrated 16 bit processor serves as a micro controller for USB peripherals. The
processor can execute approximately five million instructions per second. With this
processing power it allows the design of intelligent peripherals that can process data prior
to passing it on to the host PC, thus improving overall performance of the system. The
masked ROM (4K X 16) in the KL5KUSB101 or external memory contains a specialized
instruction set that has been designed for highly efficient coding of processing algorithms
and USB transaction processing.
The 16-bit processor is designed for efficient data execution by having direct access to
the RAM Buffer, external memory, I/O interfaces, and all the control and status registers.
The divide/multiply feature expands the capability of USB peripherals.
The processor supports prioritized vectored hardware interrupts. In addition, as many as
240 software interrupt vectors are available.
The processor provides six addressing modes, supporting memory-to-memory, memory-
to-register, register-to-register, immediate-to-register or immediate-to-memory
operations. Register, direct, immediate, indirect, and indirect indexed addressing modes
are supported. In addition, there is an auto-increment mode in which a register, used as
an address pointer is automatically incremented after each use, making repetitive
operations more efficient both from a programming and a performance standpoint.
The processor features a full set of program control, logical, and integer arithmetic
instructions. All instructions are sixteen bits wide, although some instructions require
operands, which may occupy another one or two words. Several special “ short
immediate” instructions are available, so that certain frequently used operations with
small constant operand will fit into a 16-bit instruction.
The Processor – Divide/Multiply function
The processor’s divide/multiply function contains all the instructions of the base
processor that additionally includes integer divide and multiply instructions. A signed
multiply an instruction take two 16-bit operands and returns a 32-bit result. A signed
divide instruction divides a 32-bit operand by a 16-bit operand.
RAM Buffer
The USB controller contains a 3K byte (1.5K X 16) internal buffer memory. The memory
is used to buffer data and USB packets and accessed by the 16 Bit processor and the
SIE. USB transactions are automatically routed to the memory buffer. The 16-bit
processor has the ability to set up pointers and block sizes in buffer memory for USB
transactions. Data is read from the interface and is processed and packetized by the 16-
bit I/O processor.
Ver. 2.4
Kawasaki LSI 2570 North First Street Suite 301 San Jose, CA 95131 Tel: (408) 570-0555 Fax: (408) 570-0567 www.klsi.com
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6 Page









KL5KUSB101 pdf, datenblatt
4. SRAM Interface
4.1 SRAM Read Access
KL5KUSB101
USB to Ethernet Controller
Figure 4.1.1 SRAM Read AC Timing
SRAMA14-0
(OUT)
SRAMWEN
(OUT)
SRAMOEN
(OUT)
SRAMCSN
(OUT)
SRAMD7-0
(IN)
Trc
valid
Taa
Thad
Tpoe
Toe
Tpcs
Thoe
Tacs
don't care
Thcs
valid
Table 4.1.1 SRAM Read AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Trc SRAM read cycle
31.25 –
– ns 1,2
Frc
SRAM read frequency –
– 32 MH 1,2
z
Taa SRAMA valid to
SRAMD
– – 17 ns 2
delay (address access)
Thad SRAMD hold time from
SRAMD invalid
2 – – ns 2
Tpoe SRAMOEN low width 31.25 –
– ns 2
Toe SRAMOEN assert to
SRAMD delay
– – 10 ns 2
Thoe SRAMD hold time
from SRAMOEN rise 0 – – ns 2
Tpcs SRAMCSN low width 31.25 –
– ns 1,2
Tacs SRAMCSN assert to
SRAMD delay
– – 17 ns 2
Thcs SRAMD hold time
from SRAMCSN rise 0 – – ns 2
Note: 1) Same as the USB to Ethernet internal clock cycle time 1T (31.25 ns).
2) Outputs are assumed to have 30pF external capacitive load.
Ver. 2.4
Kawasaki LSI 2570 North First Street Suite 301 San Jose, CA 95131 Tel: (408) 570-0555 Fax: (408) 570-0567 www.klsi.com
12

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