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Teilenummer | KL5BUDV003 |
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Beschreibung | USB2.0 to PCI BUS | |
Hersteller | Kawasaki | |
Logo | ||
Gesamt 6 Seiten www.DataSheet4U.com
KL5BUDV003
General Description
USB2.0 to PCI BUS
The Kawasaki KL5KBUDV003 is a high performance device that transfers data between the USB2.0
high-speed BUS and the PCI 33MHz, 32 bit BUS. This 1 chip solution has USB 2.0 transceiver
embedded reducing space and cost. The KL5KBUDV003 is an ideal solution to convert a PCI device to a
USB2.0 Transceiver, HS_SIE USB2.0 Transceiver interface, 4 sets of high-speed bulk packet size
buffers, PCI interface and PCI master 2DMA channel support.
Features
• 33MHz PCI interface
• USB 2.0 standard embedded transceiver.
• 30MHz USB 2.0 SIE BUS for High-Speed SIE
operation
• Double packet buffer - 512x2 HS, 64Bx2 FS
• Internal DMA operation between the High-Speed
SIE and Double Buffer
• High-Speed chirp protocol
• High-Speed/Full-Speed compatibility
• USB basic operation and transaction
control
• Up to 5 endpoints
• PCI interface for Target and Master (2
DMA) modes
• Page and Descriptor DMA Modes
• USB data access by PCI target or DMA
• 0.18u Std cell technology
• Vdd = 3.3V, Ta = 0~70°C
Block Diagram
USB 2.0 D+
USB 2.0 D-
KL5BUDV003
HS D+
HS D-
Rpu RPU_EN
USB 2.0
Transceiver
SIE 16 b
Rs
30 MHz
Rs
USB 2.0 SIE to PCI interface
HS_SIE DBUF
PCI IF
Clock
Generator
PCI 32 b
33 MHz
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
1
KL5BUDV003
USB2.0 to PCI BUS
Pin # I/O Pin Name
Description
QFP
99 --
GND
Ground
100 --
VDD18
1.8V power pin
101 --
GND
Ground
102 I/O
AD[11]
PCI address data bus
103 I/O
AD[10]
PCI address data bus
104 I/O
AD[9]
PCI address data bus
105 --
VDD
3.3V power pin
106 --
GND
Ground
107 I/O
AD[8]
PCI address data bus
108 I/O CBEN[0] Bus command byte enable signal
109 --
GND
Ground
110 I/O
AD[7]
PCI address data bus
111 I/O
AD[6]
PCI address data bus
112 I/O
AD[5]
PCI address data bus
113 --
VDD
3.3V power pin
114 --
GND
Ground
115 I/O
AD[4]
PCI address data bus
116 --
VDD18
1.8V power pin
117 --
GND
Ground
118 I/O
AD[3]
PCI address data bus
119 --
GND
Ground
120 I/O
AD[2]
PCI address data bus
121 I/O
AD[1]
PCI address data bus
122 --
VDD
3.3V power pin
123 I/O
AD[0]
PCI address data bus
124 --
GND
Ground
125 --
VDD
3.3V power pin
126 --
GND
Ground
127 --
VDD18
1.8V power pin
128 --
GND
Ground
129 O
CKOUT
USB CKOUT pin
130 I
VBDET
USB Vbus level detect pin
131 I
misc1
LSI shipment test pin
132 I
misc2
LSI shipment test pin
133 I/O
misc3
LSI shipment test pin
134 I/O
misc4
LSI shipment test pin
135 I/O
misc5
LSI shipment test pin
136 --
VDD18
1.8V power pin
137 --
GND
Ground
138 I/O
misc6
LSI shipment test pin
139 I/O
misc7
LSI shipment test pin
140 O
misc8
LSI shipment test pin
141 --
VDD
3.3V power pin
142 I
XIN USB Connect to external crystal oscillator
143 O
XOUT
USB Connect to external crystal oscillator
144 --
GND
Ground
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the
information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice
form Kawasaki LSI
July 2002 • Copyright 2002 • Kawasaki LSI • Printed in U.S.A
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
6
6 Page | ||
Seiten | Gesamt 6 Seiten | |
PDF Download | [ KL5BUDV003 Schematic.PDF ] |
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