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C9870G Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer C9870G
Beschreibung Clock Synthesizer
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 25 Seiten
C9870G Datasheet, Funktion
www.DataSheet4U.com
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Product Features
Supports Pentium® 4 Type CPUs
3.3 Volt Power Supply
10 Copies of PCI Clocks
3 Differential CPU Clocks
SMBus Support with Read-back Capabilities
Spread Spectrum EMI Reduction
Dial-a-Frequency™ Features
Dial-a-dB™ Features
56 Pin SSOP and TSSOP Package
Frequency Table
S2 S1 S0 CPU
3V66 66BUFF(0:2)/
66IN/
PCI_F
REF
(0:2)
3V66(0:4)
3V66-5
PCI
1 0 0 66M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 0 1 100M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 1 0 200M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 1 1 133M
66M
66IN
66MHZ clock input 66IN/2 14.318M
0 0 0 66M
66M
66M
66M
33 M
14.318M
0 0 1 100M
66M
66M
66M
33 M
14.318M
0 1 0 200M
66M
66M
66M
33 M
14.318M
0 1 1 133M
66M
66M
66M
33 M
14.318M
M 0 0 Hi-Z
Hi-Z
Hi-Z
Hi-Z Hi-Z Hi-Z
M 0 1 TCLK/2 TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
M 1 0 150M
50M
50M
50M 25M 14.318M
M 1 1 166.6M 55.5M
55.5M
55.5M
27.7M 14.318M
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
48M
48M
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PD#
SDATA
SCLK
VDDA
PLL2
WD
Logic
I2C
Logic
Power
Up Logic
REF
CPU(0:2)
CPU/(0:2)
3V66_0
3V66_1/VCH
/2 PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
66B[0:2]/3V66[2:4]
66IN/3V66-5
Pin Configuration
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF
55 S1
54 S0
53 CPU_STP#
52 CPU0
51 CPU/0
50 VDD
49 CPU1
48 CPU/1
47 VSS
46 VDD
45 CPU2
44 CPU/2
43 MULT0
42 IREF
41 VSSIREF
40 S2
39 48MUSB
38 48MDOT
37 VDD
36 VSS
35 3V66_1/VCH
34 PCI_STP#
33 3V66_0
32 VDD
31 VSS
30 SCLK
29 SDATA
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 1 of 25






C9870G Datasheet, Funktion
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Dial-a-FrequencyFeature
SMBus Dial-a-frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details
on our Dial-a-Frequency™ feature.
P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors
(S1, S0). P value may be determined from the following table:
S(1:0)
00
01
10
11
Table 1
P
32005333
48008000
96016000
64010667
Dial-a-dB™ Features
SMBus Dial-a-dB™ feature is available in this device via Byte8 and Byte9. See our App Note AN-0026 for details on
the Dial-a-dB™.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimizing Electro-Magnetic Interference (EMI) radiation
generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is
generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore
causing the average energy at any one point in this band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of
EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control
Bytes. See applications note AN-0024 for a more in depth description of Spread spectrum modulation and see the
SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the
modes and percentages of Spread Spectrum modulation that this device incorporates.
SS2 SS1
00
00
01
01
10
10
11
11
SS0
0
1
0
1
0
1
0
1
Spread Mode
Down
Down
Down
Down
Center
Center
Center
Center
Spread %
0, -1.00
0, -1.20
0, -0.50
0, -1.50
+0.50, -0.50
+0.60, -0.60
+0.25, -0.25
+0.75, -0.75
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 6 of 25

6 Page









C9870G pdf, datenblatt
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
VDD3 (3.3V +/- 5%)
Ro
Ros
Iout
Vout = 1.2V max
Iout
0V
Slope ~ 1/R0
1.2V
Vout
Host Clock (HCSL) Buffer Characteristics
Characteristic
Minimum
Maximum
Ro
3000 Ohms (recommended)
N/A
Ros
Vout
N/A
1.2V
Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage
at the pin of the device.
The various output current configurations are shown in the host swing select functions table. For all configurations, the
deviation from the expected output current is +/- 7% as shown in the current accuracy table.
CPU Clock Current Select Function
Mult0 Board Target Trace/Term Z
0 50 Ohms
1 50 Ohms
Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z
Rr = 221 1%, Iref = 5.00mA
Ioh = 4*Iref
1.0V @ 50
Rr = 475 1%, Iref = 2.32mA
Ioh = 6*Iref
0.7V @ 50
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 12 of 25

12 Page





SeitenGesamt 25 Seiten
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