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PDF C9812 Data sheet ( Hoja de datos )
| Número de pieza | C9812 | |
| Descripción | Low EMI Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Product Features
• Intel’s 810E clock solution
• 3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
• 9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
• 8 copies of PCI Clock
• 2 copies of 3V66 Clock
• 2 copies of APIC Clock, synchronous to PCI Clock
• 1 REF Clock
• 1 USB Clock (Non SSC)
• 1 DOT Clock (Non SSC)
• Power Down Feature
• Spread Spectrum Support
• SMBUS Support for turning off unused clocks
Block Diagram
Frequency Table (MHz)
SEL2 SEL1 SEL0 CPU SDRAM
PCI
X 0 0 Tristate Tristate Tristate
X01
Test mode (see table2)
0 1 0 66.6 100
33.3
0 1 1 100 100
33.3
1
1
X 133.3
100
33.3
Table 1
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=33.3MHz.
Pin Configuration
XIN
XOUT
36pF
300K
36pF
SCLK
SDATA
s2
Rin
i2c-clk
i2c-data
ioapic
cpu
SEL1
SEL0
PD#
VDD
VDD
s1
sdram
s0
pwr_dwn#
66m
PLL1
Rin
pci
48
PD#
i2c-clk
i2c-data
PLL2
Fig.1
VDD
1
REF / SEL2
VDDI
2 IOAPIC(0:1)
VDDC
3 CPU(0:2)
VDDS
9 SDRAM(0:7), DCLK
VDD
2 3V66(0:1)
VDD
8 PCI(0:7)
VDD
1 DOT
VDD
1 USB
SEL2/REF
VDD
XIN
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VSS
55 IOAPIC0
54 IOAPIC1
53 VDDI
52 CPU0
51 VDDC
50 CPU1
49 CPU2_ITP
48 VSS
47 VSS
C
46
45
SDRAM0
SDRAM1
9 44 VDDS
8 43 SDRAM2
1
42
41
SDRAM3
VSS
2 40 SDRAM4
39 SDRAM5
38 VDDS
37 SDRAM6
36 SDRAM7
35 VSS
34 DCLK
33 VDD
32 PD#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 1 of 18
1 page  
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of
the device, this pin is in input mode (see Fig 4, below), therefore; it is considered an input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.
POWER SUPPLY
RAMP
VDD RAIL
REF / SEL2
(Pin 1)
Hi-Z INPUTS
-
TOGGLE OUTPUTS
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-down each (70KΩ), therefore, a selection “0” is the default. If the
system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-down in
order to insure a low selection.
Fig. 5 If a selection “0” is desired, then a jumper is placed on JP1 to a 10KΩ resistor as implemented as shown in Fig.5.
Please note the selection resistor (Rdn) is placed before the Damping resistor (Rd) close to the pin.
Vdd JP1
Jumper
31
2
IMI C9812
Rsel
10K
Bidirectional
Rd
Load
Fig. 5
70K
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 5 of 18
5 Page 
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
AC Parameters
Symbol
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
TPeriod
Tr / Tf
TCCJ
TPeriod
Tr / Tf
TCCJ
tpZL, tpZH
tpLZ, tpZH
tstable
Parameter
CPU(0:1) period
CPU(0:1) high time
CPU(0:1) low time
CPU(0:1) rise and fall times
CPU0 to CPU1 Skew time
CPU(0:1) Cycle to Cycle Jitter
APIC(0:1) period
APIC(0:1) high time
APIC(0:1) low time
APIC(0:1) rise and fall times
APIC(0:1) Cycle to Cycle Jitter
3V66-(0:1) period
3V66-(0:1) high time
3V66-(0:1) low time
3V66-(0:1) rise and fall times
3V66-0 to 3V66-1 Skew time
3V66-(0:1) Cycle to Cycle Jitter
PCI(0:7) period
PCI(0:7) period
PCI(0:7) low time
PCI(0:7) rise and fall times
(Any PCI clock) to (Any PCI clock)
Skew time
PCI(0:7) Cycle to Cycle Jitter
48MHz period ( conforms to
+167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
REF period
REF rise and fall times
REF Cycle to Cycle Jitter
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
133 MHz Host
Min Max
7.5 8.0
1.87 -
1.67 -
0.4 1.6
- 175
- 250
60.0 -
25.5 -
25.3 -
0.4 1.6
- 500
15.0 16.0
5.25 -
5.05 -
0.4 1.6
- 250
- 500
30.0 -
12.0 -
12.0 -
0.5 2.0
- 500
100 MHz Host
Min Max
10.0 10.5
3.0 -
2.8 -
0.4 1.6
- 175
- 250
60.0 -
25.5 -
25.3
N/S
0.4 1.6
- 500
15.0 16.0
5.25 -
5.05 -
0.4 1.6
- 250
- 500
30.0 -
12.0 -
12.0 -
0.5 2.0
- 500
Units
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
nS
nS
nS
nS
pS
pS
nS
nS
nS
nS
pS
- 500 - 500
20.8299 20.8333 20.8299 20.8333
pS
nS
1.0
-
69.8413
1.0
-
1.0
1.0
4.0
500
71.0
4.0
1000
10.0
10.0
3
1.0
-
69.8413
1.0
-
1.0
1.0
4.0
500
71.0
4.0
1000
10.0
10.0
3
nS
pS
nS
nS
pS
nS
nS
mS
Notes
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
5, 6, 8
6, 7
6, 8, 9
5, 6, 8
6, 7
6, 8
13
13
12
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet C9812.PDF ] | |
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