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AZ10E111 Schematic ( PDF Datasheet ) - Arizona

Teilenummer AZ10E111
Beschreibung 1:9 Differential Clock Driver
Hersteller Arizona
Logo Arizona Logo 




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AZ10E111 Datasheet, Funktion
www.DataSheet4U.com
DATA SHEET
AZ10E111
ARIZONA MICROTEK, INC.
AZ100E111
1:9 Differential Clock Driver
FEATURES
Low Skew
Guaranteed Skew Spec
Differential Design
Enable
VBB Output
Extended 100E VEE Range of -4.2V to -5.46V
75kInternal Input Pulldown Resistors
Direct Replacement for Motorola MC10EL111 & MC100EL111
Manufactured Under License By Lucent Technologies
PACKAGE AVAILABILITY
SUFFIX DESCRIPTION
FN Plastic 28 PLCC
DESCRIPTION
The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It
accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is
fanned-out to 9 identical differential outputs. An Enable input is also provided. A HIGH disables the device by
forcing all Q outputs LOW and all QN outputs HIGH.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated
into 50, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs
on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps)
of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
VEE
ENN
Q0 Q0N Q1 VCCO Q1N
25 24 23 22 21
26
27
Q2 Q2N
20 19
18
17
Q3
Q3N
LOGIC SYMBOL
Q0
QON
IN
VCC
INN
28
1
2
Pinout: 28-Lead PLCC
(Top View)
16 Q4
15 VCCO
14 Q4N
Q1
Q1N
Q2
Q2N
VBB
NC
3
4
13 Q5
12 Q5N
5 6 7 8 9 10 11
IN
INN
ENN
Q3
Q3N
Q4
Q4N
Q8N
Q8 Q7N VCCO Q7 Q6N
Q6
PIN DESCRIPTION
PIN
IN, INN
ENN
Q0, Q0N-Q8N,
Q8
FUNCTION
Differential Input Pair
Enable
Differential Outputs
VBB Output
VBB
Q5
Q5N
Q6
Q6N
Q7
Q7N
Q8
Q8N
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