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PDF MTV212M32 Data sheet ( Hoja de datos )
| Número de pieza | MTV212M32 | |
| Descripción | 8051 Embedded Monitor Controller Flash Type | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
8051 Embedded Monitor Controller
Flash Type with ISP
FEATURES
• 8051 core, 12MHz operating frequency.
• 512-byte RAM; 32K-byte program Flash-ROM support In System Programming(ISP).
• Maximum 14 channels of 5V open-drain PWM DAC.
• Maximum 32 bi-directional I/O pins.
• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
• Built-in self-test pattern generator with four free-running timings.
• Built-in low power reset circuit.
• Compliant with VESA DDC1/2B/2Bi/2B+ standard.
• Dual slave IIC addresses.
• Single master IIC interface for internal device communication.
• 4-channel 6-bit ADC.
• Watchdog timer with programmable interval.
• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M32 micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
applications. It includes an 8051 CPU core, 512-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 3-channel A/D converter and a 32K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P2.0-2,P2.4-7
P3.2-0
P3.4-5
P0.0-
7
RD
WR
ALE
INT1
RST 8051
X1
X2
P0.0-
7
RD
WR
ALE
INT1
XFR
AD0-2 ADC
H/VSYNC
CONTROL
STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH
14 CHANNEL
PWM DAC
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.1 - 1 - 2000/07/04
1 page  
MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
PIN CONFIGURATION
A “CMOS output pin” means it can sink and drive at least 4mA current. It’s not recommended to use such pin
as input fuction.
A “5V open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used
as input or output function and need an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 100uA to maintain
the pin at high level. It can be used as input or output function. It need an external pull up resistor when drive
heavy load device.
Output
Data
2 OSC
period
delay
Output
Data
4mA
10uA
4mA
Input
Data
120uA
Pin
8051 Standard Pin
4mA
CMOS Output Pin
Pin
4mA
Input
Data
Output
Data
No Current
5V Open Drain Pin
Pin
4mA
Revision 1.1
- 5 - 2000/07/04
5 Page 
MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
6.1 Composite SYNC separation/insertion
The MTV212M32 continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212M32 can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The HBLANK
pulse can be disable or enable by setting “NoHins” control bit.
6.2 H/V Frequency Counter
MTV212M32 can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits
Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.
6.2.1 H-Freq Table
H-Freq(KHZ)
1 31.5
2 37.5
3 43.3
4 46.9
5 53.7
6 60.0
7 68.7
8 75.0
9 80.0
10 85.9
11 93.8
12 106.3
Output Value (14 bits)
12MHz OSC (hex / dec)
0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203
6.2.2 V-Freq Table
V-Freq(Hz)
1 56
2 60
3 70
4 72
5 75
6 85
Output value (12bits)
12MHz OSC (hex / dec)
45Ch / 1116
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the
CVpre flag interrupt may be disabled when S/W disable the composite function.
Revision 1.1
- 11 -
2000/07/04
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MTV212M32.PDF ] | |
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