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PDF DS1033 Data sheet ( Hoja de datos )
| Número de pieza | DS1033 | |
| Descripción | 3-in-1 Low Voltage Silicon Delay Line | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS1033
3-in-1 Low Voltage Silicon Delay Line
FEATURES
All-silicon timing circuit
Three independent buffered delays
Initial delay tolerance ±1.5 ns
Stable and precise over temperature and
voltage
Leading and trailing edge precision preserves
the input symmetry
Standard 8-pin DIP, 8-pin SOIC
Vapor phasing, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
IN1
IN2
IN3
GND
1
2
3
4
8 VCC
7 OUT1
6 OUT2
5 OUT3
DS1033M 8-Pin DIP
See Mech. Drawings Section
IN1
IN2
IN3
GND
1
2
3
4
8 VCC
7 OUT1
6 OUT2
5 OUT3
DS1033Z 8-Pin SOIC (150-mil)
See Mech. Drawings Section
PIN DESCRIPTION
IN1-IN3
- Input Signals
OUT1-OUT3
- Output Signals
NC - No Connection
VCC - Supply Voltage
GND
- Ground
(Sub)
- Internal substrate
connection, do not make
any external connections
to these pins
DESCRIPTION
The DS1033 series is a low-power +3.3 Volt version of the DS1035. It is characterized for operation
over the range of 2.7V to 3.6V.
The DS1033 series of delay lines have three independent logic buffered delays in a single package. It is
available in a standard 8-pin DIP, 150-mil 8-pin mini-SOIC.
The device features precise leading and trailing edge accuracies. It has the inherent reliability of an all-
silicon delay line solution. The DS1033’s nominal tolerance is ±1.5 ns and an additional tolerance over
temperature and voltage of ±1.0 ns for the faster delays. Detailed specifications are shown in Table 1.
Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972)
371-4348 for further information.
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TEST CONDITIONS
Ambient Temperature:
25°C ±=3°C
Supply Voltage (VCC):
Input Pulse:
3.3V ±=0.1V
High: 3.0V ±=0.1V
Low: 0.0V ±=0.1V
Source Impedance: 50Ω=max.
Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load Capacitance: 15 pF
Output:
Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
DS1033
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
TIMING DIAGRAM
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive with respect to de-coupling, layout, etc.
3. VCC=3.3V ±=10%.
4. VCC=2.7V.
5 of 6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DS1033.PDF ] | |
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