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PDF SPT7920 Data sheet ( Hoja de datos )
| Número de pieza | SPT7920 | |
| Descripción | A/D CONVERTER | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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SPT7920
12-BIT, 10 MSPS, TTL, A/D CONVERTER
FEATURES
• Monolithic
• 12-Bit 10 MSPS Converter
• 66 dB SNR @ 1 MHz Input
• On-Chip Track/Hold
• Bipolar ±2.0 V Analog Input
• Low Power (1.1 W Typical)
• 5 pF Input Capacitance
• TTL Outputs
APPLICATIONS
• Radar Receivers
• Professional Video
• Instrumentation
• Medical Imaging
• Electronic Warfare
• Digital Communications
• Digital Spectrum Analyzers
• Electro-Optics
GENERAL DESCRIPTION
The SPT7920 A/D converter is the industry's first 12-bit
monolithic analog-to-digital converter capable of sample
rates greater than 10 MSPS. On board input buffer and
track/hold function assures excellent dynamic perfor-
mance without the need for external components. Drive
requirement problems are minimized with an input ca-
pacitance of only 5 pF.
Logic inputs and outputs are TTL. An overrange output
signal is provided to indicate overflow conditions. Output
data format is straight binary. Power dissipation is very low
at only 1.1 watts with power supply voltages of +5.0 and
-5.2 volts. The SPT7920 also provides a wide input voltage
range of ±2.0 volts.
The SPT7920 is available in 32-lead ceramic sidebrazed
DIP and 44-lead cerquad packages over the commercial
temperature range. Consult the factory for availability of die,
military temperature and /883 versions.
BLOCK DIAGRAM
VIN
Input
Buffer
Analog Gain
Compression
Processor
4-Bit Flash
Converter
Track-and-Hold
Amplifiers
4
Asynchronous
SAR
8
Error
Correction,
Decoding
and
Output TTL
Drivers
12
Digital
Output
1 page  
SPECIFICATION DEFINITIONS
APERTURE DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on various
DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes at
these DC levels.
DIFFERENTIAL NONLINEARITY (DNL)
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
(normalized) from a straight line drawn from -Fs through +Fs.
The deviation is measured from the edge of each particular
code to the true straight line.
OUTPUT DELAY
Time between the clock's triggering edge and output data
valid.
DIFFERENTIAL PHASE (DP)
A signal consisting of a sine wave superimposed on various
DC levels that is applied to the input. Differential phase is the
maximum variation in the sampled sine wave phases at these
DC levels.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
N
=
SINAD -
6.02
1.76
+/- FULL-SCALE ERROR (GAIN ERROR)
Difference between measured full scale response
[(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input stage.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 125% of full scale is reduced to 50%
of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the fundamental sinusoid power to the total noise
power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total noise
and distortion power.
TOTAL HARMONIC DISTORTION (THD)
The ratio of the total power of the first 64 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
SPT7920
5 3/10/97
5 Page 
PIN ASSIGNMENTS
DGND 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8 32L Sidebrazed
D7 9
D8 10
D9 11
D10 12
D11 13
D12 14
DGND 15
DVCC 16
32 DVCC
31 VEE
30 AGND
29 VCC
28 VFB
27 VSB
26 VRT1
25 VRT2
24 VIN
23 VRT3
22 VST
21 VFT
20 VCC
19 AGND
18 VEE
17 CLK
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
N/C
1
2
3
4
5
6
7
8
9
10
11
44L Cerquad
33 N/C
32 VFB
31 VSB
30 VRT1
29 VRT2
28 VIN
27 VRT3
26 VST
25 VFT
24 N/C
23 VCC
PIN FUNCTIONS
Name
Function
DGND
Digital Ground
AGND
Analog Ground
D0-D11
TTL Outputs (D0=LSB)
D12 TTL Output Overrange
CLK Clock Input
VEE -5.2 V Supply
VCC
VRT1-VRT3
VIN
+5.0 V Supply
Voltage Reference Taps
Analog Input
DVCC
VFT
VST
Digital +5.0 V Supply (TTL Outputs)
Force for Top of Reference Ladder
Sense for Top of Reference Ladder
VFB Force for Bottom of Reference Ladder
VSB Sense for Bottom of Reference Ladder
ORDERING INFORMATION
PART NUMBER
SPT7920SCJ
SPT7920SCQ
TEMPERATURE RANGE
0 to +70 °C
0 to +70 °C
PACKAGE
32L Sidebrazed Dip
44L Cerquad
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT7920
11 3/10/97
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet SPT7920.PDF ] | |
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