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AD6624 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD6624
Beschreibung 80 MSPS Digital Receive Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD6624 Datasheet, Funktion
www.DataSheet4U.com
a
Four-Channel, 80 MSPS Digital
Receive Signal Processor (RSP)
FEATURES
80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)
Dual High Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,
EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony
PRODUCT DESCRIPTION
The AD6624 is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.
AD6624
The AD6624 is part of Analog Devices’ SoftCell® multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The AD6624 is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x, and the AD922x families of
data converters. The AD6624 is also compatible with the AD6600
Diversity ADC, providing a cost and size reduction path.
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
SYNCA
SYNCB
SYNCC
SYNCD
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
CH A
FUNCTIONAL BLOCK DIAGRAM
NCO
16 BITS
18 BITS
rCIC2
RESAMPLER
CIC5
20 BITS
24 BITS
RAM
COEFFICIENT
FILTER
CH B
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH C
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH D
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
SDIN[3:0]
SDO[3:0]
DR[3:0]
SDFS[3:0]
SDFE[3:0]
SCLK[3:0]
MODE
DS(RD)
CS
RW (WR)
DTACK(RDY)
A[2:0]
D[7:0]
EXTERNAL SYNC
CIRCUITRY
JTAG
INTERFACE
BUILT-IN
SELF-TEST
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.






AD6624 Datasheet, Funktion
AD6624
TIMING DIAGRAMS
CLK
tCLK
tCLKL
tCLKH
LIA-A
LIA-B
LIB-A
LIB-B
tDLI
Figure 1. Level Indicator Output Switching Characteristics
CLK
SCLK
tDSCLKH
tSCLKH
tSCLKL
Figure 4. SCLK Switching Characteristics (Divide by 1)
RESET
tSSF
Figure 2. RESET Timing Requirements
CLK
IN[13:0]
EXP[2:0]
tSI tHI
DATA
Figure 3. Input Data Timing Requirements
CLK
tDSCLKH
SCLK
tSCLKL
Figure 5. SCLK Switching Characteristic (Divide by 2 or
EVEN Integer)
CLK
SCLK
tDSCLKH
tDSCLKLL
Figure 6. SCLK Switching Characteristic (Divide by 3 or
ODD Integer)
SCLK
SDFS
SDI
SDFE
tDSDFS
tSSI
tHSI
DATAn
tDSDFE
Figure 7. Serial Port Switching Characteristics
–6– REV. B

6 Page









AD6624 pdf, datenblatt
AD6624
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
92
93
94
95
97
98
99
100
101
104
105
106
107
109
110
111
112
114
115–117
119–122
124–127
Mnemonic
SCLK11
SDFS11
SDO11
SDIN11
SDFE1
DR1
SCLK21
SDFS21
SDO21
SDIN21
SDFE2
DR2
SCLK31
SDFS31
SDO31
SDIN31
SDFE3
DR3
EXPB[0:2]1
INB[13:10]1
INB[9:6]1
Type
I/O
I/O
O/T
I
O
O
I/O
I/O
O/T
I
O
O
I/O
I/O
O/T
I
O
O
I
I
I
NOTES
1Pins with a pull-down resistor of nominal 70 k.
2Pins with a pull-up resistor of nominal 70 k.
Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-State.
Function
Bidirectional Serial Clock—Channel 1
Bidirectional Serial Data Frame Sync—Channel 1
Serial Data Output—Channel 1
Serial Data Input—Channel 1
Serial Data Frame End—Channel 1
Output Data Ready Indicator—Channel 1
Bidirectional Serial Clock—Channel 2
Bidirectional Serial Data Frame Sync—Channel 2
Serial Data Output—Channel 2
Serial Data Input—Channel 2
Serial Data Frame End—Channel 2
Output Data Ready Indicator—Channel 3
Bidirectional Serial Clock—Channel 3
Bidirectional Serial Data Frame Sync—Channel 3
Serial Data Output—Channel 3
Serial Data Input—Channel 3
Serial Data Frame End—Channel 3
Output Data Ready Indicator—Channel 3
B Input Data (Exponent)
B Input Data (Mantissa)
B Input Data (Mantissa)
–12–
REV. B

12 Page





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