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PDF NCP1337 Data sheet ( Hoja de datos )
| Número de pieza | NCP1337 | |
| Descripción | PWM Current Mode Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP1337
PWM Current-Mode
Controller for Free Running
Quasi-Resonant Operation
The NCP1337 combines a true current mode modulator and
a demagnetization detector which ensures full Borderline/Critical
Conduction Mode in any load/line conditions together with
minimum drain voltage switching (Quasi−Resonant operation).
The transformer core reset detection is done internally, without using
any external signal, due to the Soxyless concept. The frequency is
internally limited to 130 kHz, preventing the controller to operate
above the 150 kHz CISPR−22 EMI starting limit.
By monitoring the feedback pin activity, the controller enters skip
mode as soon as the power demand falls below a predetermined
level. As each restart is softened by an internal Soft−Skipt, and as
the frequency cannot go below 25 kHz, no audible noise can be
heard.
The NCP1337 also features an efficient protective circuitry which,
in presence of an overcurrent condition, disables the output pulses
and enters a safe burst mode, trying to restart. Once the default has
gone, the device auto−recovers. Also included is a bulk voltage
monitoring function (known as brown−out protection), an adjustable
overpower compensation, and a VCC OVP. The controller
immediately restarts after any of these conditions, unless the fault
timer has timed out. Finally, an internal 4.0 ms soft−start eliminates
the traditional startup stress.
Features
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
• Current−Mode
• Soft−Skip Mode with Minimum Switching Frequency for Standby
• Auto−Recovery Short−Circuit Protection Independent of Auxiliary
Voltage
• Overvoltage Protection
• Brown−Out Protection
• Two Externally Triggerable Fault Comparators (one for a disable
function, and the other for a permanent latch)
• Internal 4.0 ms Soft−Start
• 500 mA Peak Current Drive Sink Capability
• 130 kHz Max Frequency
• Internal Leading Edge Blanking
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• Dynamic Self−Supply with Levels of 12 V (On) and 10 V (Off)
• SPICE Models Available for TRANsient and AC Analysis
• These are Pb−Free Devices
Typical Applications
• AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
www.onsemi.com
PDIP−7
P SUFFIX
CASE 626B
MARKING
DIAGRAM
7
NCP1337P
AWL
YYWWG
1
SOIC−7
D SUFFIX
CASE 751U
8
P1337
ALYW G
G
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
BO
2
FB
3
CS
4
GND
8
HV
6
VCC
5
DRV
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1337PG
PDIP−7
(Pb−Free)
50 Units/Rail
NCP1337DR2G
SOIC−7 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 6
1
Publication Order Number:
NCP1337/D
1 page  
NCP1337
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V, unless otherwise noted.)
Characteristic
Pin Symbol Min Typ Max
SUPPLY SECTION
VCC Increasing Level at which the Controller Starts
VCC Decreasing Level at which the Controller Stops
Protection Mode is Activated if VCC reaches this Level whereas the HV
Current Source is ON
6
6
6
VCCON
VCCMIN
VCCOFF
11 12 13
9.0 10 11
− 9.0 −
VCC Decreasing Level at which the Latch−Off Phase Ends
Margin between VCC Level at which Latch Fault is Released and
VCCLATCH
VCC Increasing Level at which the Controller Enters Protection Mode
VCC Level below which HV Current Source is Reduced
Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz
Internal IC Consumption, Latch−Off Phase, VCC = 8.0 V
Internal IC Consumption in Skip
INTERNAL STARTUP CURRENT SOURCE
Minimum Guaranteed Startup Voltage on HV Pin
High−Voltage Current Source when VCC > VCCINHIB
(VCC = 10.5 V, VHV = 60 V)
High−Voltage Current Source when VCC < VCCINHIB
(VCC = 0 V, VHV = 60 V)
Leakage Current Flowing when the HV Current Source is OFF
(VCC = 17 V, VHV = 500 V)
6 VCCLATCH 3.6 5.0 6.0
− VMARGIN 0.3 − −
6
VCCOVP
17.6 18.6 19.6
6 VCCINHIB − 1.5 −
6 ICC1 − 1.2 −
6 ICC2 − 2.0 −
6 ICC3 − 600 −
6 ICCLOW − 600 −
8 VHVmin − − 55
8 IC1 5.5 9.5 15
8 IC2 0.3 0.6 1.1
8 IHVLeak − − 90
DRIVE OUTPUT
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal
5
TR
− 50 −
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 TF − 20 −
Source Resistance
5 ROH − 20 −
Sink Resistance
5 ROL − 8.0 −
TEMPERATURE SHUTDOWN
Temperature Shutdown
−
TSD
130 −
−
Hysteresis on Temperature Shutdown
− − − 30 −
CURRENT COMPARATOR
Maximum Internal Current Setpoint (@ IFB = IFB100%)
Minimum Internal Current Setpoint (@ IFB = IFBrippleIN)
Internal Current Setpoint for IFB = IFBrippleOUT
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
Internal Current Offset Injected on the CS Pin during ON Time
(Over Power Compensation)
@ 1.0 V on Pin 1 and Vpin3 = 0.5 V
@ 2.0 V on Pin 1 and Vpin3 = 0.5 V
Maximum ON Time
3
VCSLimit
475 500 525
3 VCSrippleIN − 100 −
3 VCSrippleOUT −
130 −
3 TDEL − 120 150
3 TLEB − 350 −
3 IOPC
− 35 −
− 105 −
5
MaxTON
52 67 82
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
V
mA
mA
mA
ns
ns
W
W
°C
°C
mV
mV
mV
ns
ns
mA
ms
www.onsemi.com
5
5 Page 
NCP1337
Soxyless
The “Valley point detection” is based on the observation
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the VIN asymptote
is governed by the resonating energy transfer between the
LP transformer inductor and the global capacitance present
on the Drain. These voltage oscillations create current
oscillation in the parasitic capacitor across the switching
MOSFET (modelized by the Crss capacitance between
Gate and Drain): a negative current (flowing out of DRV
pin) takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part.
The Drain valley corresponds to the inversion of the
current (i.e., the zero crossing): by detecting this point, we
always ensure a true valley turn−on.
Isoxy
DRV
Crss
Lprim
Vswitch
TSWING
Figure 6. Soxyless Concept
t
The current in the Power MOSFET gate is:
Igate = Vringing/Zc (with Zc the capacitance impedance)
so
Igate = Vringing S (2 S p S Fres S Crss)
The magnitude of this gate current depends on the
MOSFET, the resonating frequency and the voltage swing
present on the Drain at the end of the plateau voltage.
The dead time TSWING is given by the equation:
Tswing + 0.5ńFres + p * ǸLp * Cdrain (eq. 1)
(where LP is the primary transformer inductance and
CDRAIN the total capacitance present on the MOSFET
Drain. This capacitance includes the snubber capacitor if
any, the transformer windings stray capacitance plus the
parasitic MOSFET capacitances COSS and CRSS).
Internal Feedback Circuitry
To simplify the implementation of a primary regulation,
it is necessary to inject a current into the FB pin (instead of
sourcing it out). But to have a precise primary regulation,
the voltage present on FB pin must be regulated. Figure 8
gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
and a voltage regulator.
FB
+
+
3V
-
Vdd
Internal
Setpoint
20 kHz
Low−pass Filter
Figure 7. Internal Implementation of FB Pin
www.onsemi.com
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCP1337.PDF ] | |
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