Datenblatt-pdf.com


ADV7183B Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7183B
Beschreibung Multiformat SDTV Video Decoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7183B Datasheet, Funktion
www.DataSheet4U.com
Multiformat SDTV Video Decoder
ADV7183B
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 10-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™), signal
processing, and enhanced FIFO management give mini-
TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
Chroma transient improvement (CTI)
Digital noise reduction (DNR)
Multiple programmable analog input formats
Composite video (CVBS)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
12 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or 16-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
GENERAL DESCRIPTION
The ADV7183B integrated video decoder automatically detects
and converts a standard analog baseband television signal-
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data-compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog
video characteristics, including tape-based sources, broadcast
sources, security/surveillance cameras, and professional
systems.
The 10-bit accurate A/D conversion provides professional
quality video performance and is unmatched. This allows true
8-bit resolution in the 8-bit output mode.
The 12 analog input channels accept standard composite,
S-Video, YPrPb video signals in an extensive number of
0.5 V to 1.6 V analog signal input range
Differential gain: 0.5% typ
Differential phase: 0.5° typ
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for close captioning, WSS, CGMS, EDTV,
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
2 temperature grades: 0°C to +70°C and –40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
AVR receivers
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length variation.
The output control signals allow glueless interface connections
in almost any application. The ADV7183B modes are set up
over a 2-wire, serial, bidirectional port (I2C-compatible).
The ADV7183B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7183B is packaged in a small 80-lead LQFP
Pb-free package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.






ADV7183B Datasheet, Funktion
ADV7183B
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless
otherwise specified.
Table 1.
Parameter1,
0F
2
1F
STATIC PERFORMANCE
Symbol Test Conditions
Resolution (each ADC)
N
Integral Nonlinearity
INL BSL at 54 MHz
Differential Nonlinearity
DNL BSL at 54 MHz
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
Pins listed in Note 3
2F
All other pins
Input Capacitance
DIGITAL OUTPUTS
CIN
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
VOH ISOURCE = 0.4 mA
VOL ISINK = 3.2 mA
ILEAK
Pins listed in Note 4
3F
All other pins
Output Capacitance
POWER REQUIREMENTS5
4F
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Power-Up Time
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
IPWRDN
tPWRUP
CVBS input6
5F
YPrPb input7
6F
1Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).
2The min/max specifications are guaranteed over this range.
3 Pins 36 and 79.
4 Pins 1, 2, 5, 6, 8, 12, 17, 18 to 24, 32 to 35, 74 to 76, 80.
5 Guaranteed by characterization.
6 ADC1 powered on.
7 All three ADCs powered on.
Min Typ
Max
–0.475/+0.6
–0.25/+0.5
10
±3
–0.7/+2
2
0.8
–50 +50
–10 +10
10
2.4
0.4
50
10
20
1.65 1.8
3.0 3.3
1.65 1.8
3.15 3.3
82
2
10.5
85
180
1.5
20
2
3.6
2.0
3.45
Unit
Bits
LSB
LSB
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
Rev. B | Page 6 of 100

6 Page









ADV7183B pdf, datenblatt
ADV7183B
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
3, 9, 14, 31, 71
DGND
39, 40, 47, 53, 56 AGND
4, 15 DVDDIO
10, 30, 72
DVDD
50 AVDD
38 PVDD
42, 44, 46, 58, 60,
62, 41, 43, 45, 57,
59, 61
AIN1 to AIN12
11 INTRQ
Type
G
G
P
P
P
P
I
O
13, 16 to 18, 25, 34,
35, 63, 65, 69, 70,
77, 78
33, 32, 24, 23, 22,
21, 20, 19, 8, 7, 6, 5,
76, 75, 74, 73
2
1
80
67
68
66
NC
P0 to P15
HS
VS
FIELD
SDA
SCLK
ALSB
O
O
O
O
I/O
I
I
64
RESET
I
27
LLC1
O
26
LLC2
O
29
XTAL
I
28
XTAL1
O
36
PWRDN
I
79 OE I
37
ELPF
I
12 SFL O
51
52
48, 49
54, 55
REFOUT
O
CML O
CAPY1, CAPY2 I
CAPC1, CAPC2 I
Description
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 83.
13H
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I2C address for the ADV7183B. ALSB set to Logic 0 sets the address for a
write as 0x40; for ALSB set to logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7183B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally
27 MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an
external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal
mode, the crystal must be a fundamental crystal.
A logic low on this pin places the ADV7183B in a power-down mode. Refer to the IP2PC
134H
Register Maps section for more options on power-down modes for the ADV7183B.
When set to a logic low, OE enables the pixel output bus, P15 to P0 of the ADV7183B. A
logic high on the OE pin places Pins P15 to P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 46.
135H
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
Internal Voltage Reference Output. Refer to Figure 46 for a recommended capacitor network
136H
for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 46 for a
137H
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for
138H
this pin.
ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for
139H
this pin.
Rev. B | Page 12 of 100

12 Page





SeitenGesamt 30 Seiten
PDF Download[ ADV7183B Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADV7183AMultiformat SDTV Video DecoderAnalog Devices
Analog Devices
ADV7183BMultiformat SDTV Video DecoderAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche