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NB4L858M Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB4L858M
Beschreibung Dual Differential Clock/Data 2x2 Crosspoint Switch
Hersteller ON Semiconductor
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Gesamt 10 Seiten
NB4L858M Datasheet, Funktion
NB4L858M
2.5V/3.3V, 3 GHz Dual
Differential Clock/Data 2x2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4L858M is a high−bandwidth low voltage fully differential
dual 2 x 2 crosspoint switch with CML outputs that is suitable for
applications such as SDH/SONET DWDM and high speed switching
applications. Design technique minimizes jitter accumulation,
crosstalk, and signal skew which make this device ideal for
loop−through and protection channel switching application. Each
2 x 2 crosspoint switch can fan out and/or multiplex up to 3 Gb/s data
and 3 GHz clock signals.
Differential inputs incorporate a pair of internal 50 W termination
resistors in a center−tapped configuration (VTDx Pins) and can accept
LVPECL (Positive ECL) or CML input signal without any external
component. This feature provides transmission line termination
on−chip, at the receiver end, eliminating external components.
Differential 16 mA CML output provides matching internal 50 W
terminations, and 400 mV output swings when externally terminated,
50 W to VCC.
The SELECT inputs are single−ended and can be driven with either
LVCMOS or LVTTL input levels. The device is housed in a low
profile 7 x 7 mm 32−pin LQFP package.
Features
Maximum Input Clock Frequency 3 GHz
Maximum Input Data Frequency 3 Gb/s
350 ps Typical Propagation Delay
80 ps Typical Rise and Fall Times
12 ps Channel to Channel Skew
0.5 ps RMS Jitter
5 ps Deterministic Jitter @ 2.5 Gb/s
Operating Range: VCC = 2.3V to 3.6 V with GND = 0 V
CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
These are Pb−Free Devices
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MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
NB4L
858M
AWLYYWW
32
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SELA0
DA0
VTDA0
DA0
50W
50W
SELA1
DA1
VTDA1
DA1
50W
50W
0
QA0
A0
QA0
1
0
QA1
A1
QA1
1
SELB0
0
DB0
VTDB0
DB0
50W
50W
QB0
B0
QB0
1
SELB1
0
DB1
VTDB1
DB1
50W
50W
QB1
B1
QB1
1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 9
1
Publication Order Number:
NB4L858M/D






NB4L858M Datasheet, Funktion
NB4L858M
Table 6. AC CHARACTERISTICS VCC = 2.3 V to 3.6 V, GND = 0 V; (Note 4)
−40°C
25°C
85°C
Symbol
VOUTPP
fDATA
tPLH,
tPHL
tSWiITCH
tSKEW
Characteristic
Output Voltage Amplitude (@ VINPPmin)
fin 2 GHz
(See Figure 2)
fin 3 GHz
fin 3.5GHz
Maximum Operating Data Rate
Propagation Delay to Output Differential
D/D to Q/Q
SELyx to Valid Qyx Output (Note 9)
Within −Device Skew (Note 5)
Within −Device Skew (Note 6)
Device to Device Skew (Note 9)
Min Typ Max Min Typ Max Min Typ Max Unit
280 365
235 310
170 220
280 365
235 310
170 220
280 365
235 310
170 220
mV
3 3 3 Gb/s
220 350 450 220 350 450 220 350 450
ps
0.5 1.0
0.5 1.0
0.5 1.0 ns
12 12 12 ps
25 25 25
100 100 100
tJITTER RMS Random Clock Jitter (Note 8) fin =2 GHz
0.5
0.5
0.5 ps
fin =3 GHz
1.0
1.0
1.0
Peak−to−Peak Data Dependent Jitter fin =2.5Gb/s
2.0
5.0
2.0
(Note 9)
fin =3.2Gb/s
10
10
10
Crosstalk Induced RMS Jitter (Note 11)
0.5 0.5 0.5
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration)
100 800 100 800 100 800 mV
tr Output Rise/Fall Times @ 0.5 GHz Qx, Qx
tf (20% − 80%)
80 120
80 120
80 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
5. Worst−case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively),
when both outputs come from the same input.
6. Worst−case difference between QA and QB outputs, when DA or DB inputs are shorted.
7. Additive RMS jitter with 50% duty cycle input clock signal.
8. Additive peak−to−peak data dependent jitter with input NRZ data signal.
9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
10. LVTTL/LVCMOS input edge rate less than 1.5 ns
11. Data taken on the same device under identical condition.
400
−40°C
350
85°C
300
25°C
250
200
150
100
50
0
1
1.5 2
2.5 3
3.5
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature
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