|
|
Teilenummer | NB4L16M |
|
Beschreibung | Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 12 Seiten www.DataSheet4U.com
NB4L16M
2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
Termination
Description
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
(see Table 6 and Figures 20, 21 22, and 23).
Differential inputs incorporate internal 50 W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50 W termination, and 400 mV output swing when externally
receiver terminated, 50 W to VCC (see Figure 19). These features
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For single−ended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
re−bias capacitor coupled differential or single−ended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 3.5 GHz
• Maximum Input Data Rate up to 5.0 Gb/s
• < 0.7 ps Maximum Clock RMS Jitter
• < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
• 220 ps Typical Propagation Delay
• 60 ps Typical Rise and Fall Times
• CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output),
Differential Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• Pb−Free Packages are Available
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4L
16M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VCC
VTD
50 W
D
D
50 W
VTD
R1
R2
R2
R1
Q
Q
VEE
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 1
1
Publication Order Number:
NB4L16M/D
NB4L16M
TYPICAL OPERATING CHARACTERISTICS
450
400
350
300
250
200
150
100
50
0
0
+85°C
+25°C
−40°C
2 2.5 3 3.5 4 4.5 5 5.5
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP)
vs. Input Clock Frequency (fin) and
Temperature at 3.3 V Power Supply
450
400
350 −40°C
300 +85°C
250
200
150
100 +25°C
50
0
0 2 2.5 3 3.5 4 4.5 5 5.5
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP)
vs Input Clock Frequency (fin) and
Temperature at 2.5 V Power Supply
90
80
70
VCC = 3.3 V
60
50 VCC = 2.5 V
40
30
−40 25 85
TEMPERATURE (°C)
Figure 5. Rise/Fall Time vs Temperature and
Power Supply
265
255
245
235 VCC = 3.3 V
225
215
205
195 VCC = 2.5 V
185
175
−40
25
85
TEMPERATURE (°C)
Figure 6. Propagation Delay vs Temperature
and Power Supply
http://onsemi.com
6
6 Page NB4L16M
PACKAGE DIMENSIONS
D
PIN1 ÇÇÇÇÇÇ
LOCATION
16 PIN QFN
CASE 485G−01
ISSUE B
A
B
E
0.15 C
0.15 C
TOP VIEW
0.10 C
16 X 0.08 C
(A3)
SIDE VIEW
A1
A
SEATING
PLANE
C
16X L
NOTE 5
D2
e
58
EXPOSED PAD
0.575
0.022
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.18 0.30
D 3.00 BSC
D2 1.65 1.85
E 3.00 BSC
E2 1.65 1.85
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
SOLDERING FOOTPRINT*
3.25
0.128
0.30
0.012
EXPOSED PAD
16X K
4
1
9
E2
12 e
3.25
0.128
1.50
0.059
16
16X b
13
0.10 C A B BOTTOM VIEW
0.05 C NOTE 3
0.30
0.50 0.012
ǒ Ǔ0.02
SCALE 10:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
12
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NB4L16M/D
12 Page | ||
Seiten | Gesamt 12 Seiten | |
PDF Download | [ NB4L16M Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
NB4L16M | Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator | ON Semiconductor |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |