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NB3N3011 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3N3011
Beschreibung PureEdge Clock Generator
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 7 Seiten
NB3N3011 Datasheet, Funktion
www.DataSheet4U.com
NB3N3011
3.3 V 100 MHz / 106.25 MHz
PureEdge Clock Generator
with LVPECL Differential
Output
Description
The NB3N3011 is a Fibre Channel Clock Generator and uses a
26.5625 MHz crystal to synthesize 106.25 MHz or a 25 MHz crystal
to synthesize 100 MHz. The NB3N3011 has excellent <1 ps phase
jitter performance over the 637 kHz – 10 MHz integration range. The
NB3N3011 is packaged in an 8Pin 4.4 mm x 3.0 mm TSSOP, making
it ideal for use in systems with limited board space.
Features
PureEdge Clock Family Provides Accuracy and Precision
One Differential LVPECL Output
Crystal Oscillator Interface Designed for Fundamental Mode 18 pF
Parallel Resonant Crystal (25 MHz or 26.5625 MHz)
Output Frequency: 106.25 MHz (26.5625 MHz Crystal) or 100 MHz
(25 MHz Crystal)
VCO Range: 760 MHz 950 MHz
RMS Phase Jitter @ 100 MHz, using a 25 MHz Crystal
(637 kHz 10 MHz): 0.29 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase noise:
Offset Noise Power
100 Hz 108 dBc/Hz
1 kHz 122 dBc/Hz
10 kHz 135 dBc/Hz
100 kHz 135 dBc/Hz
3.3 V Power Supply
40°C to 85°C Ambient Operating Temperature
These are PbFree Devices*
http://onsemi.com
MARKING
DIAGRAM
TSSOP8
DT SUFFIX
CASE 948S
311
YWW
AG
A = Assembly Location
Y = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
25 MHz
XIN
or
26.5625 MHz XOUT
Crystal
Oscillator
Phase
Detector
Charge
Pump
M = B32
VCO
850 MHz
w/26.5625
MHz Ref.
N =B8
LVPECL
Output
Q 100 MHz
or
Q 106.25 MHz
Figure 1. Logic Diagram
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 Rev. 0
1
Publication Order Number:
NB3N3011/D






NB3N3011 Datasheet, Funktion
NB3N3011
PC Board Layout Example
Figure 11 shows a representative board layout for the
NB3N3011. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or throughhole HC49 package. The
footprints of other components in this example are listed in
Table 9. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between VCC and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3011 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
The voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
Table 9. Footprint Table
Reference
C1, C2
C3
C4, C5
R2
Size
0402
0805
0603
0603
C2
C1
Figure 11. PC Board Layout
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping
NB3N3011DTG
TSSOP8 4.4 mm
(PbFree)
100 Units / Rail
NB3N3011DTR2G
TSSOP8 4.4 mm
(PbFree)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
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