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ADM1041 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1041
Beschreibung Secondary-Side Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 64 Seiten
ADM1041 Datasheet, Funktion
www.DataSheet4U.com
PRODUCT FEATURES
Digital calibration via internal EEPROM
Supports SSI specification
Comprehensive fault detection
Reduced component count on secondary side
Standalone or microcontroller control
SECONDARY-SIDE FEATURES
Generates error signal for primary-side PWM
Output voltage adjustment and margining
Current sharing
Current limit adjustment
OrFET control
Programmable soft-start slew rate
Standalone or microcontroller operation
Differential load voltage sense
AC mains undervoltage detection (ac sense)
Overvoltage protection
RS
PWM
CONTROLLER
VDD
VDD
VDD
BIAS
VDD
THERMISTOR
OTP
Secondary-Side Controller with
Current Share and Housekeeping
ADM1041
INTERFACE AND INTERNAL FEATURES
SMBus interface (I2C compatible)
Low-drift precision 2.5 V reference
Voltage error amplifier
Differential current sense
Sense resistor or current transformer option
Overvoltage protection
Undervoltage protection
Overcurrent protection
Overtemperature protection
Start-up undervoltage blanking
Programmable digital debounce and delays
352-byte EEPROM available for field data
160-byte EEPROM for calibration
Ground continuity monitoring
APPLICATIONS
Network servers
Web servers
Power supply control
OrFET
VOUT
RLOAD
VDD
ADM1041
CBD
FG
CS–/VLS
CS+
VDD
VCMP
ICT
FD
SHRO
SHRS
VS+
VS
PULSE AC_OK
MON2 DC_OK
PEN
PSON
CCMP
SCMP
ADD0
SCL
GND
SDA
GND
SHARE BUS
VDD
VOUT
VS+
VS
MICRO-
CONTROLLER
OPTIONAL
ISOLATION BARRIER
Figure 1. Typical Application Circuit
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADM1041 Datasheet, Funktion
ADM1041
SPECIFICATIONS
TA = –40 to +85°C, VDD = 5 V ± 10%, unless otherwise noted.
Table 1.
Parameter
Min Typ
Max
SUPPLIES
VDD
IDD, Current Consumption
Peak IDD, during EEPROM Erase Cycle1, 2
4.5 5.0
6
5.5
10
40
UNDERVOLTAGE LOCKOUT, VDD
Start-Up Threshold
4 4.3
4.5
Stop Threshold
3.7 4
4.2
Hysteresis
0.3
VREF, 2.5 VREFOUT
Output Voltage
2.49 2.50
2.51
Line Regulation
–5 0
+5
Load Regulation
–5 0
+5
Temperature Stability2
±100
Long-Term Stability2
±5
Current Limit
10 20
Output Resistance2
0.5
Load Capacitance
1
Ripple Due to Autozero2
±5
POWER BLOCK PROTECTION
VDD Overvoltage
VDD Overvoltage Debounce
VREF Overvoltage
5.8 6.2
10
2.9
6.5
20
VREFOUT Undervoltage
2.1
Open Ground
0.1 0.2
0.35
Debounce
100 200
POWER-ON RESET
DC Level
1.5 2.2
2.75
DIFFERENTIAL LOAD VOLTAGE SENSE INPUT,
(VS−, VS+)
VS− Input Voltage
VS+ Input Voltage
VS− Input Resistance
VS+ Input Resistance
VNOM Adjustment Range
0.5
VDD – 2
35
500
1.7 to 2.3
Set Load Voltage Trim Step
0.10 to 0.14
1.74 –> 3.18
Set Load Overvoltage Trim Range
Set Load Overvoltage Trim Step
105 to 120
0.09
1.6
Recover from Load OV False to FG True
Operate Time from Load OV to FG False
100
200
300
400
2
Unit
V
mA
mA
V
V
V
V
mV
mV
ppm/°C
mV
mA
nF
mV p-p
V
µs
V
V
V
µs
V
V
V
kΩ
kΩ
V
%
mV
%
%
mV
µs
µs
µs
µs
µs
Test Conditions/Comments
See Figure 9.
Reg 0Fh[4:2] = 111. See Table 24.
IREF = 1 mA, TA = 25°C
4.5 V ≤ VDD ≤ 5.5 V
0 mA ≤ IREF ≤ 2 mA
IREF = 1 mA
Over 1,000 hr, TJ = 125°C
VREF = 2.4 V
Recommended for stability
VREF refreshed at 30 kHz
Latching
Internal
External
VGND positive with respect to VS
VDDOK
VDD rising
See Figure 6. VNOM = (VS+ – VS−)
VNOM is typically 2 V
Voltage on Pin 20
Voltage on Pin 21
1.7 V ≤ VNOM ≤ 2.3 V typ
8 bits, 255 steps
Reg 19h[7:0]. See Table 34
1.7 V ≤ VNOM ≤ 2.3 V min
8 bits, 255 step/s
Reg 08h[7:0]. See Table 17.
VS+ = 2.24 V
Reg 03h[1:0] = 00. See Table 12.
Reg 03h[1:0] = 01. See Table 12.
Reg 03h[1:0] = 10. See Table 12.
Reg 03h[1:0] = 11. See Table 12.
Rev. A | Page 6 of 64

6 Page









ADM1041 pdf, datenblatt
ADM1041
1 This specification is a measure of IDD during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical IDD plot during an EEPROM page
erase.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are
RTOP
RBOTTOM
3.3 V
680R
1K
5.0 V
1K.5
1K
12 V
5K1
1K
4 Chopper off.
5 The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.
6 All internal amplifiers accept inputs with common range from GND to VDD − 2 V. The output is rail to rail but the input is limited to GND to VDD − 2 V. See Figure 6.
7 These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity. Refer to Table 45.
8 A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.
9 Endurance is qualified to 100,000 cycles as per JEDEC std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 250,000 cycles.
10 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V. Derates
with junction temperature.
SCL
tLOW tR
tHD:STA
tHD:DAT
SDA
tBUF
PS
tF
tHIGH
tSU:DAT
tHD:STA
tSU:STA
S
Figure 5. Serial Bus Timing Diagram
tSU:STO
P
SHRO
SHRS+
SHRS–
VA VA = VDD – 0.4V
R1
VB VB = VDD – 2V
R1
R1 + R2 1k
Figure 6. Amplifier Inputs and Outputs
Rev. A | Page 12 of 64

12 Page





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