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PDF XQ4000XL Data sheet ( Hoja de datos )
| Número de pieza | XQ4000XL | |
| Descripción | QML High-Reliability FPGAs | |
| Fabricantes | Xilinx | |
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QPRO XQ4000XL Series QML
High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
02
XQ4000X Series Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
• Ceramic and plastic packages
• Also available under the following standard microcircuit
drawings (SMD)
- XQ4013XL 5962-98513
- XQ4036XL 5962-98510
- XQ4062XL 5962-98511
- XQ4085XL 5962-99575
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• Available in -3 speed
• System featured Field-Programmable Gate Arrays
- SelectRAM™ memory: on-chip ultra-fast RAM with
· synchronous write option
· dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System performance beyond 50 MHz
• Flexible array architecture
• Low power segmented routing architecture
• Systems-oriented features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000XL output
• Configured by loading binary file
- Unlimited reprogrammability
• Readback capability
- Program verification
- Internal node observability
Product Specification
• Development system runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
• Highest capacity—over 180,000 usable gates
• Additional routing over XQ4000E
- Almost twice the routing capacity for high-density
designs
• Buffered Interconnect for maximum speed
• New latch capability in configurable logic blocks
• Improved VersaRing™ I/O interconnect for better Fixed
pinout flexibility
- Virtually unlimited number of clock signals
• Optional multiplexer or 2-input function generator on
device outputs
• 5V tolerant I/Os
• 0.35 µm SRAM process
Introduction
The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits of custom CMOS VLSI, while avoiding
the initial cost, long development cycle, and inherent risk of
a conventional masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000XL Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
Global Buffer Switching Characteristics
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Symbol
TGLS
Description
Delay from pad through Global Low Skew buffer, to any
clock K
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
All -3 -1
Min Max Max Units
0.6 3.6
-
ns
1.1 4.8
-
ns
1.4 6.3
-
ns
1.6 - 5.7 ns
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Symbol
TGE
Description
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
All -3 -1
Min Max Max Units
0.4 2.4
-
ns
0.3 3.1
-
ns
0.3 4.9
-
ns
0.4 - 4.7 ns
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol
TGE
Description
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
All -3 -1
Min Max Max Units
0.7 2.4
-
ns
0.9 4.7
-
ns
1.2 5.9
-
ns
1.3 - 5.5 ns
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
Symbol
Description
Device
All -3 -1
Min Max Max Units
TICKOF Global low skew clock to output using OFF(4)
XQ4013XL
1.5
8.6
-
ns
XQ4036XL
2.0
9.8
- ns
XQ4062XL
2.3
11.3
-
ns
XQ4085XL
2.5
-
9.5 ns
TSLOW For output SLOW option add
All Devices
3.0
3.0
3.0 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
3. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
4. OFF = Output Flip-Flop
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
Symbol
Description
Device
All -3 -1
Min Max Max Units
TICKEOF Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6.
XQ4013XL
XQ4036XL
1.3
1.2
7.4
8.1
- ns
- ns
XQ4062XL
1.2
9.9
- ns
XQ4085XL
1.3
-
8.5 ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet XQ4000XL.PDF ] | |
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