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PDF CY7C016 Data sheet ( Hoja de datos )
| Número de pieza | CY7C016 | |
| Descripción | (CY7C006 / CY7C016) 16K x 8/9 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.comwith Sem, Int,Busy
CY7C006
CY7C016
Features
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
• 16K x 8 organization (CY7C006)
• 16K x 9 organization (CY7C016)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 140 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7C016) TQFP
• Pin compatible and functional equivalent to
IDT7006/IDT7016
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
16K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
schemes are included on the CY7C006/016 to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and du-
al-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags, BUSY and INT, are provided on each port. BUSY signals
that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Enable (CE) pin
or SEM pin.
The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.
Logic Block Diagram
R/WL
CEL
OEL
R/W R
CE R
OER
(7C016) I/O 8L
I/O7L
I/O0L
BUSYL[1,2]
A 13L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O8R (7C016)
I/O 7R
I/O 0R
[1,2]
BUSYR
A 13R
A0R
CE L
OEL
R/W L
SEM L
INTL [2]
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CER
OER
R/W R
SEMR
INTR[2]
C006-1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 22, 1999
1 page  
CY7C006
CY7C016
Electrical Characteristics (continued)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
VIL Input LOW Voltage
IIX Input Leakage Current GND ≤ VI ≤ VCC
IOZ Output Leakage Current Outputs Disabled, GND ≤ VO ≤ VCC
ICC
Operating Current
VCC = Max., IOUT = 0 mA
Com’l
Outputs Disabled
Ind
ISB1
Standby Current
(Both Ports TTL Levels)
Cf =ELfMaAnXd[5C] ER ≥ VIH,
Com’l
Ind
ISB2
Standby Current
(One Port TTL Level)
Cf =ELfMoArXC[5E] R ≥ VIH,
Com’l
Ind
ISB3 Standby Current
Both Ports
Com’l
(Both Ports CMOS
Levels)
CE and CER ≥ VCC – 0.2V,
oVrINV≥INV≤C0C.2–V0, .f2=V0[5]
Ind
ISB4 Standby Current
One Port
Com’l
(One Port CMOS Level) CEL or CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or
Ind
VPoINrt≤O0u.2tpVu,tAs,cfti=vefMAX[5]
7C006-35
7C016-35
7C006-55
7C016-55
Min. Typ. Max. Min. Typ. Max. Unit
2.4 2.4
V
0.4 0.4 V
2.2 2.2
V
0.8 0.8 V
–10 +10 –10 +10 µA
–10 +10 –10 +10 µA
150 210
140 200 mA
150 250
140 240
30 50
20 40 mA
30 65
20 55
80 120
70 100 mA
80 130
70 115
3 15
3 15 mA
3 15
3 15
70 100
70 110
60 90 mA
60 95
Capacitance[6]
CIN
COUT
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
5V
5V
OUTPUT
C = 30 pF
R1=893Ω
R2=347Ω
OUTPUT
C=30 pF
RTH =250Ω
VTH =1.4V
OUTPUT
C = 5 pF
R1=893Ω
R2=347Ω
(a) Normal Load (Load 1)
C006-5
(b) Thévenin Equivalent (Load)
C006-6
OUTPUT
C = 30 pF
3.0V
GND
10%
ALL INPUT PULSES
90%
90%
10%
Load (Load 2)
C006-8
≤ 3 ns
≤ 3 ns
C006-9
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
(c) Three-State Delay (Load 3)
C006-7
5
5 Page 
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[29]
CELValid First:
ADDRESSL,R
ADDRESS MATCH
CE L
CE R
BUSYR
tPS
tBLC
CERValid First:
ADDRESSL,R
ADDRESS MATCH
CER
CEL
BUSYL
tPS
tBLC
tBHC
tBHC
Busy Timing Diagram No. 2 (Address Arbitration)[28]
Left AddressValid First:
ADDRESSL
ADDRESSR
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESS MATCH
tPS
tBLA
ADDRESSR
ADDRESSL
BUSYL
tRC or tWC
ADDRESS MATCH
tPS
tBLA
ADDRESS MISMATCH
tBHA
ADDRESS MISMATCH
tBHA
Notes:
29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
30. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
CY7C006
CY7C016
C006-19
C006-20
C006-21
C006-22
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C016.PDF ] | |
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