PDF CY7C4292 Data sheet ( Hoja de datos )

Número de pieza	CY7C4292
Descripción	(CY7C4282 / CY7C4292) 64K/128K x 9 Deep Sync FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY7C4282 CY7C4292 Features 64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion Functional Description • High-speed, low-power, first-in first-out (FIFO) memories • 64K × 9 (CY7C4282) • 128K × 9 (CY7C4292) • 0.5-micron CMOS for optimum speed/power • High-speed, near-zero latency (true dual-ported memory cell), 100-MHz operation (10-ns read/write cycle times) • Low power — ICC=40 mA — ISB = 2 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, and Programmable Almost Empty and Almost Full status flags • TTL-compatible • Retransmit function • Output Enable (OE) pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width-Expansion Capability • Depth-Expansion Capability through token-passing scheme (no external logic required) • 64-pin 10 × 10 STQFP The CY7C4282/CY7C4292 are high-speed, low-power, FIFO memories with clocked read and write interfaces. All devices are nine bits wide. The CY7C4282/CY7C4292 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write-enable pin (WEN). Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (XI), cascade output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4282/92 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Logic Block Diagram D0-8 INPUT REGISTER WCLK WEN WRITE CONTROL RS FL/RT XI/LD PAF/XO WRITE POINTER RESET LOGIC EXPANSION LOGIC Dual Port RAM Array 64K x 9 128K x 9 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAE PAF/XO THREE-STATE OUTPUT REGISTER Q0 − 8 OE READ CONTROL RCLK REN Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-06009 Rev. B Revised August 21, 2003 1 page CY7C4282 CY7C4292 Programmable Almost Empty/Almost Full Flag The CY7C4282/CY7C4292 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. Table 2. Status Flags Number of Words in FIFO CY7C4282 CY7C4292 0 1 to n[2] 0 1 to n[2] (n + 1) to (65536 − (m + 1)) (65536 − m)[3] to 65535 (n + 1) to (131072 − (m + 1)) (131072 − m)[3] to 131071 65536 131072 FF PAF HH HH HH HL LL PAE EF LL LH HH HH HH Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incriminated until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are trans- mitted also. The full depth of the FIFO can be repeatedly retransmitted. Width-Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demon- strates a 18-bit word width by using two CY7C4282/92. Any word width can be attained by adding additional CY7C4282/92. When the CY7C4282/92 is in a Width-Expansion Configu- ration, the Read Enable (REN) control input can be grounded (see Figure 2). In this configuration, the Load (LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Notes: 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value). Document #: 38-06009 Rev. B Page 5 of 16 5 Page Switching Waveforms (continued) Reset Timing [16] [17] LD tRSS tRS RS REN, WEN EF,PAE FF,PAF Q0 – Q8 tRSF tRSF tRSF tRSR First Data Word Latency after Reset with Simultaneous Read and Write CY7C4282 CY7C4292 [18] OE=1 OE=0 WCLK D0 –D8 WEN RCLK EF tDS tENS D0 (FIRSTVALID WRITE) [19] tFRL tSKEW1 D1 tREF D2 D3 D4 REN Q0 –Q8 OE tOLZ tA tOE [20] tA D0 D1 Note: 4282–9 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. For standalone or width expansion configuration only. 18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1. 19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 20. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06009 Rev. B Page 11 of 16 11 Page

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