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PDF ADM1191 Data sheet ( Hoja de datos )
| Número de pieza | ADM1191 | |
| Descripción | Digital Power Monitor | |
| Fabricantes | Analog Devices | |
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Data Sheet
Digital Power Monitor
with Convert Pin and ALERTB Output
ADM1191
FEATURES
Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Convert (CONV) pin for commanding an ADC read
SETV input for setting overcurrent alert threshold
ALERTB output provides an overcurrent interrupt
I2C fast mode-compliant interface (400 kHz maximum)
2 address pins allow 16 devices on the same bus
10-lead MSOP
APPLICATIONS
Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1191 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip
12-bit analog-to-digital converter (ADC), communicated
through an I2C® interface.
An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.
A 12-bit ADC can measure the current seen in the sense
resistor, as well as the supply voltage on the VCC pin.
An industry-standard I2C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I2C command or via the convert (CONV) pin.
The CONV pin is especially useful for synchronizing reads on
multiple ADM1191 devices. Alternatively, the ADC can run
continuously, and the user can read the latest conversion data
whenever it is required. Up to 16 unique I2C addresses can be
created, depending on the way the A0 pin and the A1 pin are
connected.
A SETV pin is also included. A voltage applied to this pin is
internally compared with the output voltage on the current
sense amplifier. The output of the SETV comparator asserts
when the current sense amplifier output exceeds the SETV
voltage. When this event occurs, the ALERTB output asserts.
FUNCTIONAL BLOCK DIAGRAM
ADM1191
CONV
VCC
V
0
SENSE
A
CURRENT
SENSE
AMPLIFIER
I
1
MUX
12-BIT
ADC
SDA
I2C SCL
A1
A0
SETV
COMPARATOR
ALERT
GND
Figure 1.
ALERTB
3.15V TO 26V
RSENSE
VCC SENSE
ALERTB
ADM1191
SETV
SDA
SCL
CONV
GND
A1
A0
CONTROLLER
INTERRUPT
P = VI
SDA
SCL
CONV
Figure 2. Applications Diagram
The ALERTB output can be used as a flag to warn a micro-
controller or field programmable gate array (FPGA) of an
overcurrent condition. ALERTB outputs of multiple ADM1191
devices can be tied together and used as a combined alert.
The ADM1191 is packaged in a 10-lead MSOP.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
1 page  
ADM1191
Data Sheet
Parameter
A0 PIN, A1 PIN
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
Min
0
80
Set Address to 10, IADRHIGHZ
−0.3
Set Address to 11, VADRHIGHV
Input Current for 00 Decode, IADRLOW
Input Current for 11 Decode, IADRHIGH
I2C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
Output Fall Time on SDA from VIHMIN to VILMAX
Maximum Width of Spikes Suppressed by
Input Filtering on SDA and SCL Pins
Input Current, II, on SDA/SCL When Not
Driving a Logic Low Output
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, tSU;STA
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
Capacitive Load for Each Bus Line
2
−40
0.7 VBUS
20 + 0.1 CBUS
50
−10
600
1300
600
100
600
1300
Typ
120
−25
3
5
Max Unit Conditions
0.8 V Low state
160 kΩ Resistor to ground state, load pin with
specified resistance for 01 decode
+0.3 µA Open state, maximum load allowed
on the A0 pin or A1 pin for 10 decode
5.5 V High state
µA VADR = 0 V to 0.8 V
6 µA VADR = 2.0 V to 5.5 V
0.3 VBUS
0.4
250
250
V
V
V
ns
ns
VBUS = 3.0 V to 5.5 V
VBUS = 3.0 V to 5.5 V
IOL = 3 mA
CBUS = bus capacitance from SDA to GND
+10 µA
pF
400 kHz
ns
ns
ns
900 ns
ns
ns
400 pF
1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
2 This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see
the specifications for the Current Sense Absolute Accuracy parameter).
3 These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
specifications for the Voltage Sense Accuracy parameter).
4 Time between the receipt of the command byte and the actual ADC result being placed in the register.
Rev. C | Page 4 of 16
5 Page 
ADM1191
Data Sheet
Base Address
A1 Pin State
Floating
Floating
High
High
High
High
1 X = don’t care.
A0 Pin State
Floating
High
Ground
Resistor to ground
Floating
High
A1 Pin Logic State
10
10
11
11
11
11
A0 Pin Logic State
10
11
00
01
10
11
Address in Binary1
0111010X
0111011X
0111100X
0111101X
0111110X
0111111X
Address in Hex
0x74
0x76
0x78
0x7A
0x7C
0x7E
SCL
1
91
9
SDA
01
START BY MASTER
SCL
(CONTINUED)
1
1 A1A A1B A0A
FRAME 1
SLAVE ADDRESS
A0B R/W
D7
ACKNOWLEDGE BY
SLAVE
9
D6 D5 D4 D3 D2 D1 D0
FRAME 2
COMMAND CODE
ACKNOWLEDGE BY
SLAVE
1
9
SDA
(CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACKNOWLEDGE BY
SLAVE
D7 D6 D5 D4 D3 D2 D1 D0
FRAME N
DATA BYTE
ACKNOWLEDGE BY
SLAVE
STOP
BY
MASTER
Figure 16. General I2C Write Timing Diagram
SCL
1
91
9
SDA
01
START BY MASTER
SCL
(CONTINUED)
1
1 A1A A1B A0A
FRAME 1
SLAVE ADDRESS
A0B R/W
D7
ACKNOWLEDGE BY
SLAVE
9
D6 D5
1
D4 D3 D2
FRAME 2
DATA BYTE
D1 D0
ACKNOWLEDGE BY
MASTER
9
SDA
(CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACKNOWLEDGE BY
MASTER
D7 D6 D5 D4 D3 D2 D1 D0
FRAME N
DATA BYTE
NO ACKNOWLEDGE
STOP
BY
MASTER
Figure 17. General I2C Read Timing Diagram
SCL
tLOW
tR
tHD;STA
tHD;DAT
SDA
tBUF
PS
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 18. Serial Bus Timing Diagram
tSU;STO
P
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADM1191.PDF ] | |
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