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S71WS512P Schematic ( PDF Datasheet ) - SPANSION

Teilenummer S71WS512P
Beschreibung Migrating from the S71WS512N to the S71WS512P
Hersteller SPANSION
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Gesamt 18 Seiten
S71WS512P Datasheet, Funktion
www.DataSheet4U.com
S71WS512N to S71WS512P
Migrating from the S71WS512N to the S71WS512P
Application Note
by Daisuke Nakata
1. Introduction
Migrating from the S71WS512N to the monolithic S71WS512P is a simple process; however, the user should be aware of a few
differences between these two parts. These differences are the result of the S71WS512N using two S29WS256N die in series
while the S71WS512P uses a single S29WS512P configuration. This application note describes these differences in detail so
users currently using the S71WS512N configuration can plan ahead and include the necessary software to ensure a smooth
migration to the S71WS512P. Both software and hardware considerations are covered. Table 1.1 shows a comparison of the
key features between the two flash device cores.
Table 1.1 Comparison of Key Features
Futures
Technology
Process Rule
VCC
VIO (VCCQ)
Max Density
Configuration Register
Sector Architecture
Bank Architecture
Bank Size
Boot Option
Common Flash Interface (CFI)
Simultaneous Read/Write
Asynchronous Read Mode
Page Mode Read
Page Size
Synchronous (Burst) Read Mode
Burst Frequency
Burst Length
Single Word / Write Buffer Program
Write Buffer Size
Program Suspend / Program Resume
Sector Erase / Chip Erase
Erase Suspend / Erase Resume
Unlock Bypass / Fast Mode
Accelerated Program / Chip Erase
Sector Protection
Secured Silicon Area
S29WS256N
MirrorBit
110 nm
1.70 V to 1.95 V
=VCC
256 Mb
CR0-CR15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
2 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
4-words
Yes
54 MHz / 66 MHz / 80 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
S29WS512P
MirrorBit
90 nm
1.70 V to 1.95 V
=VCC
512 Mb
CR0.0 - CR0.15, CR1.0 - CR1.15
16 K-words Small Sector
64 K-words Large Sector
16 Bank Structure
4 Mb
Top / Bottom / Dual
Yes
Yes
Yes
Yes
8-words
Yes
54 MHz / 66 MHz / 80 MHz / 108 MHz
8 / 16 / 32 Continuous
Yes
32-words
Yes
Yes
Yes
Yes
Yes
Hardware: WP#
Software: ASP
128-words factory locked
128-words customer lockable
Publication Number 2xWS-N_to_WS-P_AN
Revision 01E
Issue Date October 3, 2006






S71WS512P Datasheet, Funktion
Application Note
Table 4.3 Configuration Register Access Command Comparison
Command
Set Configuration Register
S29WS256N
Read Configuration Register
Set Configuration Register
S29WS512P
Read Configuration Register
First
Cycles Addr Data
4 555 AA
4 555 AA
5 555 AA
4 555 AA
Second
Addr Data
2AA 55
2AA 55
2AA 55
2AA 55
Bus Cycles
Third
Fourth
Addr Data Addr
Data
555 D0
X00
CR
555 C6
X00
CR
555 D0
X00
CR0
555 C6 X0 or X1 CR0 or CR1
Fifth
Sixth
Addr Data Addr Data
X01 CR1
Figure 4.2 shows an example of how to set the configuration register for 80 MHz 8-Burst with Wrap Read (7-
Wait), RDY Active-H 1 cycle prior.
Figure 4.2 Example Configuration Register Settings
Cycle Operation
6:61
Byte
Address
Word
Address
Data
Cycle Operation
6:63
Byte
Address
Word
Address
Data
 :ULWH %$$$$K %$K $$K  :ULWH %$$$$K %$K $$K
 :ULWH %$K %$$$K K
 :ULWH %$K %$$$K K
 :ULWH %$$$$K %$K 'K
 :ULWH %$$$$K %$K 'K
 :ULWH %$
%$K &5 )&$K 
:ULWH %$
%$K &5 )&$K
 :ULWH %$  K %$  K &5 ))((K
&5 %LW
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5 
9DOXH
















+H[ 9DOXH

)
&
$
&5 %LW
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5 
9DOXH
















+H[ 9DOXH

)
&
$
&5 %LW
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5
&5 
9DOXH
















+H[ 9DOXH
)
)
(
(
4.5 Page Mode Read
Both devices are capable of page mode reads, which provides random read access speed for locations within
a page. Table 4.4 shows the page size comparison differences between the S71WS512N and the
S71WS512P.
6
S71WS512N to S71WS512P
2xWS-N_to_WS-P_AN_01E October 3, 2006

6 Page









S71WS512P pdf, datenblatt
Application Note
Table 6.2 S29WS512P Asynchronous Read
Parameter
Description
tCE
tACC
Access Time from CE# Low
Asynchronous Access Time
tAVDP
tAAVDS
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
tAAVDH
Address Hold Time from Rising Edge of AVD#
tOE
tOEH
tOEZ
tCAS
tPACC
Output Enable to Output Valid
Output Enable Hold
Time
Read
Toggled and Data#
Polling
Output Enable to High Z
CE# Setup Time to AVD#
Intra Page Access Time
Mode
Zero Hold
Legacy
Zero Hold
Legacy
Zero Hold
Legacy
Zero Hold
Legacy
54 MHz 66 MHz 80 MHz
83
Max
80
83
Max
80
Min 8
8
8
Min 4
4
4
Min 8
8
8
Min 7
6
6
Min 0
0
0
Max 6
Min 0
0
0
108 MHz
7.5
3.5
7.5
4
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min 10
10
10
6 ns
Max 10
Min 0
Max 20
10
0
20
10
0
20
7 ns
0 ns
20 ns
Table 6.3 S29WS256N Synchronous Burst Read
Parameter
tIACC
tBACC
tACS
tACH
tBDH
tRDY = tCR
tOE
tCEZ
tOEZ
tCES
tRACC
tCAS
tAVC
tAVD
Description
Synchronous Access Time
Burst Access Time Valid Clock to Output Delay
Address Setup Time to Clock
Address Hold Time from Clock
Data Hold Time
Chip Enable to RDY Active
Output Enable to RDY Low
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to Clock
Ready Access Time from Clock
CE# Setup Time to AVD#
AVD# Low to Clock Setup Time
AVD# Pulse
Mode
54 MHz 66 MHz 80 MHz 108 MHz Unit
Max 80
— ns
Max 13.5
11.2
9
— ns
Min 5 4 — ns
Min 7 6 — ns
Min 4 3 — ns
Max 13.5
11.2
9
— ns
Max 13.5
11.2
— ns
Max 10
— ns
Max 10
— ns
Min 4
— ns
Max 13.5
11.2
9
— ns
Min 0
— ns
Min 4
— ns
Min 8
— ns
12
S71WS512N to S71WS512P
2xWS-N_to_WS-P_AN_01E October 3, 2006

12 Page





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