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S71WS256P Schematic ( PDF Datasheet ) - SPANSION

Teilenummer S71WS256P
Beschreibung Burst Mode Flash Memory
Hersteller SPANSION
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Gesamt 10 Seiten
S71WS256P Datasheet, Funktion
www.DataSheet4U.com
S71WS-P based MCP Products
1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode
Flash Memory with CellularRAM
Data Sheet (Advance Information)
S71WS-P based MCP Products Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-P_00 Revision A Amendment 2 Issue Date August 21, 2006






S71WS256P Datasheet, Funktion
Data Sheet (Advance Information)
3.3
NOR Flash and pSRAM Input/Output Descriptions
Amax-A0
DQ15-DQ0
F-CE#
OE#
WE#
F-VCC
F-VCCQ
VSS
RFU
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE#
R-CRE
R-VCC
R-UB#
R-LB#
DNU
= NOR Flash Address inputs
= Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND
= NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode.
= Output Enable input. Asynchronous relative to CLK for Burst mode.
= Write Enable input.
= NOR Flash device power supply (1.7 V - 1.95V).
= Input/Output Buffer power supply.
= Ground
= Reserved for Future Use
= Flash ready output. Indicates the status of the Burst read. VOL = data valid. The Flash RDY pin is shared
with the WAIT pin of the pSRAM.
= NOR Flash Clock, shared with CLK of burst-mode pSRAM.. The first rising edge of CLK in conjunction
with AVD# low latches the address input and activates burst mode operation. After the initial word is
output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low
during asynchronous access.
= NOR Flash Address Valid input. Shared with AVD# of burst-mode pSRAM. Indicates to device that the
valid address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched on rising edge of CLK.
VIH= device ignores address inputs
= NOR Flash hardware reset input. VIL= device resets and returns to reading array data
= NOR Flash hardware write protect input. VIL = disables program and erase functions in the four
outermost sectors.
= NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
= Chip-enable input for pSRAM
= Control Register Enable (pSRAM). For CellularRAM only.
= pSRAM Power Supply
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
= Do Not Use
4
S71WS-P based MCP Products
S71WS-P_00_A2 August 21, 2006

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