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S71WS128N Schematic ( PDF Datasheet ) - SPANSION

Teilenummer S71WS128N
Beschreibung Stacked Multi-Chip Product (MCP)
Hersteller SPANSION
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Gesamt 13 Seiten
S71WS128N Datasheet, Funktion
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S71WS-N
Stacked Multi-Chip Product (MCP)
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with CellularRAM
Data Sheet (Advance Information)
S71WS-N Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-N_00
Revision A Amendment 6
Issue Date July 19, 2006






S71WS128N Datasheet, Funktion
Data Sheet (Advance Information)
3. Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
A23-A0
DQ15-DQ0
OE#
WE#
VSS
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F1-CE#
F2-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
Description
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal
address counter. Should be at VIL or VIH while in asynchronous mode
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be
at VIH for all other conditions.
Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL,
disables all program and erase functions. Should be at VIH for all other conditions.
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only.
Control Register Enable (pSRAM). For CellularRAM only.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
4
S71WS-N
S71WS-N_00_A6 July 19, 2006

6 Page









S71WS128N pdf, datenblatt
Data Sheet (Advance Information)
5.3.4
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm
0.15 C
(2X)
D
PIN A1
CORNER
INDEX MARK
10
TOP VIEW
A A2
A D1
eD
10
9
8
7
E
6
5
4
eE 3
2
1
B
0.15 C
(2X)
0.20 C
ML K J HG F E D C B A
7
SD
BOTTOM VIEW
SE 7
E1
PIN A1
CORNER
A1
6
SIDE VIEW
84X b
0.15 M C A B
0.08 M C
C
PACKAGE
JEDEC
FEA 084
N/A
DxE
SYMBOL
A
A1
A2
D
E
D1
E1
MD
ME
n
Øb
eE
eD
SD / SE
12.00 mm x 9.00 mm
PACKAGE
MIN
NOM
MAX
--- --- 1.40
0.10 ---
---
1.11 --- 1.26
12.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
10
84
0.35 0.40 0.45
0.80 BSC.
0.80 BSC
0.40 BSC.
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
BALL DIAMETER
BALL PITCH
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
Note:
BSC is an ANSI standard for Basic Space Centering.
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
10
S71WS-N
S71WS-N_00_A6 July 19, 2006

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