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PDF EPXA4 Data sheet ( Hoja de datos )
| Número de pieza | EPXA4 | |
| Descripción | Excalibur Devices | |
| Fabricantes | Altera Corporation | |
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Excalibur EPXA4 Devices
November 2002, ver. 1.2
Errata Sheet
This errata sheet provides updated information about the Excalibur™
EPXA4, revision A (see Figure 1) Devices.
Figure 1. Identify Revision A Devices
Revision Number
The errata fall into two categories:
■ Known errata for the EPXA4 device—detailed in this document
■ Known errata for the ARM922T processor provided by ARM Ltd.—
detailed in Appendix A of this document
The following sections of the device are covered by errata information:
■ Expansion bus interface (EBI)
■ Dual-port SRAM (DPRAM)
■ AHB bridges
■ UART
■ SDRAM
■ Embedded trace module version 2a
■ Configuration
■ Debug module
Contact Altera® for the latest information.
Altera Corporation
ES-EPXA4-1.2
1
1 page  
Excalibur EPXA4 Devices Errata Sheet
UART
This section provides further information about errata in the UART.
4.1 UART State Undefined Following Reset
When the device comes out of reset, the UART may sometimes generate a
modem interrupt and behave as though a character has been received.
SDRAM
Work Around
To avoid generating a modem interrupt, clear all interrupts and flush the
receive and transmit FIFO buffers before interrupts from the UART are
enabled.
This section provides further information about errata in the SDRAM.
5.1 32-bit DDR SDRAM Memories are Not Supported
The SDRAM controller in the ARM-based family (including the EPXA4)
does not support interfacing with 32-bit DDR SDRAM devices that use the
A8 address line for the command sequence. Also 32-bit DDR memories
have one DQS pin; ARM-based devices require four (one per byte).
Memories that use the A10 address line for the command sequence and
have one DQS pin per byte are supported.
5.2 Improper DDR SDRAM Data Accesses for Certain Clock Ratios
Incorrect data may result from DDR SDRAM accesses if the AHB1 or
AHB2 master clock is greater than 4 times faster than the SDRAM clock,
SD_CLK.
Embedded
Trace Module
Version 2a
Work Around
Ensure that the AHB1/2 clock frequency is less than or equal to 4 times the
SDRAM clock frequency.
EPXA4 devices include the ARM ETM9 version 2a. Please see the
ETM9_Rev_2a_Errata.doc for errata on this version of the ETM9. This
document is available on the ARM Limited website.
Version 2a has a different configuration code register value compared to
version 1, which is used in the EPXA10 devices. The ARM Trace Tools
version 1.1 does not support ETM9 version 2a. Support will be included
in a new version of the trace tools planned for Q2 2002.
Altera Corporation
5
5 Page 
Errata Sheet - Appendix A
Conditions
Extended wait-state periods can be caused by cache misses in cached
systems, or the use of a slow memory system. Consequently, the problem
is unlikely to occur in uncached systems or in systems where the speed of
the memory is close to that of the processor. Since the clock speed on the
ARM920T and ARM922T processors is slowed to that of the memory
when a cache miss occurs, memory speed is not an issue on these
processors, and consequently this erratum is less likely to occur on
systems with these devices.
The block data transfer instruction must be executing when the overflow
occurs. The instructions which fall into this category are as follows:
■ ARM instructions:
LDM, STM, SWP, SWPB, LDC, STC, LDRD, STRD, MCRR, MRRC.
■ Thumb instructions:
POP, PUSH, LDMIA, STMIA.
The wait-state period must begin before the overflow occurs. It is possible
for an overflow to occur after the wait-state has begun due to trace
continuing to enter the FIFO from the ETM pipeline. The wait-state period
must continue until after the ETM has recovered from the overflow,
having drained its FIFO of all pending trace.
The problem is more likely to occur with a small FIFO than a large FIFO
for two reasons:
■ A smaller FIFO is more likely to overflow.
■ Once an overflow has occurred, a smaller FIFO takes less time to
drain. Consequently, the length of the extended wait-state period
required for the problem to occur is reduced.
As a result, the problem is most likely to occur with the small ETM
configuration, and least likely with the large ETM configuration.
The minimum number of cycles required to drain the FIFO, and therefore
the theoretical minimum length of the wait-state period, is shown in
Table 3 on page 12.
Altera Corporation
11
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