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ZL38004 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL38004
Beschreibung Dedicated Voice Processor
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 7 Seiten
ZL38004 Datasheet, Funktion
www.DataSheet4U.com
ZL38004
Dedicated Voice Processor
with Dual Channel Codec
Data Sheet
A full Design Manual is available to qualified
customers. To register, please send an email to
Features
• 100 MHz (200 MIPs) Zarlink voice processor with
Butterfly hardware accelerator and
breakpoint/interrupt controller
• On-board Data (26 Kbytes), Instruction (24
Kbytes RAM and Boot (3 Kbytes) ROM
• Dual ∆Σ ADCs with input buffer gain selection
programmable to either 8 or 16 kHz sampling
• Dual ∆Σ DACs with output sampling of 8, 16, 44.1
and 48 kHz and internal output driver
• 2048 tap Filter co-processor shared across up to
16 separate functions in 128 tap increments
• Dual function Inter-IC Sound (I2S) or Secondary
TDM port
June 2006
Ordering Information
ZL38004QCG1 100 Pin LQFP Trays, Bake &
Drypack
*Pb Free Matte Tin
-40°C to +85°C
• Primary PCM port supports TDM (ST BUS, GCI or
McBSP framing) or SSI modes at bit rates of 128,
256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
• Separate slave (microcontroller) and master
(Flash) SPI ports, maximum clock rate = 25 MHz
• Watchdog and 2 auxiliary timers
• 11 General Purpose Input/Output (GPIO) pins
• General purpose UART port
• Bootloadable for future Zarlink software upgrades
• External oscillator or crystal/ceramic resonator
• 1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
• IEEE-1149.1 compatible JTAG port
Buffer
Driver
Buffer
CODEC[0]
ADC
DAC
IRQ
CODEC[1]
ADC
DAC
IRQ[15:0]
Interrupt
Controller
DSP
Core
Driver
IRQ
5
/ PCM P0
IRQ
ButterFly
Hardware
Accelerator
100 MHz MCLK
Instruction
RAM
APLL
OSC
24K
Bytes
3K Boot
Bytes ROM
Data RAM
27K
Bytes
PCM P0
Clock
Chain
JTAG
Timing
Generator
CODEC[1:0]
Device Clocks
IRQ
IRQ Master
SPI
IRQ Slave
SPI
IRQ
5
/
I2S
IRQ
IRQ APLL
Watchdog
IRQ
UART
IRQ
PCM P1
Filter
Co-processor
MCLK
AUX Timer1
AUX Timer2
IRQ
IRQ
GPIO
OSCo
OSCi
PCM_CLKi
PCM_LBCi
5
/
5
/
4
/
2
/
11
/
Figure 1 - Functional Block Diagram
3
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.






ZL38004 Datasheet, Funktion

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