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QT60326 Schematic ( PDF Datasheet ) - QUANTUM

Teilenummer QT60326
Beschreibung (QT60326 / QT60486) 32 & 48 KEY QMATRIX ICs
Hersteller QUANTUM
Logo QUANTUM Logo 




Gesamt 30 Seiten
QT60326 Datasheet, Funktion
www.DataSheet4U.com
lQ
QT60326, QT60486
32 & 48 KEY QMATRIX™ ICs
z Advanced second generation QMatrix™ controller
z Keys individually adjustable for sensitivity, response
time, and many other critical parameters
z Panel thicknesses to 50mm through any dielectric
z 32 and 48 key versions
z 100% autocal for life - no in-field adjustments
z SPI Slave and UART interfaces
z Sleep mode with wake pin
z Adjacent key suppression feature
z Synchronous noise suppression pin
z Spread-spectrum modulation: high noise immunity
z Mix and match key sizes & shapes in one panel
z Low overhead communications protocol
z FMEA compliant design features
z Negligible external component count
z Extremely low cost per key
z 44-pin Pb-free TQFP package
MOSI
MISO
SCK
/RST
Vdd
Vss
XT2
XT1
RX
TX
WS
144 43 42 41 40 39 38 37 36 35 3343
2 32
3 31
4 QT60326 30
5 QT60486 29
6 28
7
8
TQFP-44
27
26
9 25
10 24
11
12
13
14
15
16
17
18
19
20
23
21 22
Y3B
Y2B
Y1B
Y0B
Vdd
Vss
Vdd
X7
X6
X5
X4
APPLICATIONS -
y Security keypanels
y Industrial keyboards
y Appliance controls
y Outdoor keypads
y ATM machines
y Touch-screens
y Automotive panels
y Machine tools
These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up 48 keys when used with a scanned,
passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, and even wood, up to
thicknesses of 5 cm or more. The touch areas are defined as simple 2-part interdigitated electrodes of conductive material, like copper
or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and placement are almost entirely arbitrary;
sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area. The sensitivity of
each key can be set individually via simple functions over the SPI or UART port, for example via Quantum’s QmBtn program, or from a
host microcontroller. Key setups are stored in an onboard eeprom and do not need to be reloaded with each powerup.
These devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, or
similar products that are subject to environmental influences or even vandalism. It can permit the construction of 100% sealed,
watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel surface
from abrasion, chemicals, or abuse. To this end the device contains Quantum-pioneered adaptive auto self-calibration, drift
compensation, and digital filtering algorithms that make the sensing function robust and survivable.
The parts can scan matrix touch keys over LCD panels or other displays when used with clear ITO electrodes arranged in a matrix.
They do not require 'chip on glass' or other exotic fabrication techniques, thus allowing the OEM to source the matrix from multiple
vendors. Materials such as such common PCB materials or flex circuits can be used.
External circuitry consists of a resonator and a few passive parts, all of which can fit into a 6.5 sq cm footprint (1 sq inch). Control and
data transfer is via either an SPI or UART port.
These devices make use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that
minimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.
TA
-400C to +1050C
-400C to +1050C
AVAILABLE OPTIONS
# Keys
Part Number
32 QT60326-AS-G
48 QT60486-AS-G
LQ
Copyright © 2003-2005 QRG Ltd
QT60486-AS R8.01/0105






QT60326 Datasheet, Funktion
2-5). Only one key along a particular X line needs to be
observed, as each of the keys along that X line will be identical.
The chosen dwell time should exceed the observed 95%
settling of the X-pulse by 25% or more.
In almost all case, Ry should be set equal to Rx, which will
ensure that the charge on the Y line is fully captured into the Cs
capacitor.
2.9 Key Design
Circuits can be constructed out of a variety of materials
including flex circuits, FR4, and even inexpensive single-sided
CEM-1.
The actual internal pattern style is not as important as is the
need to achieve regular X and Y widths and spacings of
sufficient size to cover the desired graphical key area or a little
bit more; ~3mm oversize is acceptable in most cases, since the
key’s electric fields drop off near the edges anyway. The overall
key size can range from 10mm x 10mm up to 100mm x 100mm
but these are not hard limits. The keys can be any shape
including round, rectangular, square, etc. The internal pattern
can be as simple as a single bar of Y within a solid perimeter of
X, or (preferably) interdigitated as shown in Figure 2-6.
For better surface moisture suppression, the outer perimeter of
X should be as wide as possible, and there should be no
ground planes near the keys. The variable ‘T’ in this drawing
represents the total thickness of all materials that the keys must
penetrate.
See Figure 2-6 and page 30 for examples of key layouts.
2.10 PCB Layout, Construction
It is best to place the chip near the touch keys on the same
PCB so as to reduce X and Y trace lengths, thereby reducing
the chances for EMC problems. Long conn ection traces act as
RF antennae. The Y (receive) lines are much more susceptible
to noise pickup than the X (drive) lines.
Even more importantly, all signal related discrete parts (R’s and
C’s) should be very close to the body of the chip. Wiring
between the chip and the various R’s and C’s should be as
short and direct as possible to suppress noise pickup.
Ground planes and traces should NOT be used around the
keys and the Y lines from the keys. Ground areas, traces, and
other adjacent signal conductors that act as AC ground (such
as Vdd and LED drive lines etc) will absorb the received key
signals and reduce signal-to-noise ratio (SNR) and thus will be
counterproductive. Ground planes around keys will also make
water film effects worse.
Ground planes, if used, should be placed under or around the
QT chip itself and the associated R’s and C’s in the circuit,
under or around the power supply, and back to a connector, but
nowhere else.
See page 30 for an example of a 1-sided PCB layout.
2.10.1 LED Traces and Other Switching Signals
Digital switching signals near the Y lines will induce transients
into the acquired signals, deteriorating the SNR perfomance of
the device. Such signals should be routed away from the Y
lines, or the design should be such that these lines are not
switched during the course of signal acquisition (bursts).
LED terminals which are multiplexed or switched into a floating
state and which are within or physically very near a key
structure (even if on another nearby PCB) should be bypassed
to either Vss or Vdd with at least a 10nF capacitor of any type,
to suppress capacitive coupling effects which can induce false
signal shifts. Led terminals which are constantly connected to
Vss or Vdd do not need further bypassing.
2.10.2 PCB Cleanliness
All capacitive sensors should be treated as highly sensitive
circuits which can be influenced by stray conductive leakage
paths. QT devices have a basic resolution in the femtofarad
range; in this region, there is no such thing as ‘no clean flux’.
Flux absorbs moisture and becomes conductive between
solder joints, causing signal drift and resultant false detections
or transient losses of sensitivity or instability. Conformal
coatings will trap in existing amounts of moisture which will then
become highly temperature sensitive.
The designer should specify ultrasonic cleaning as part of the
manufacturing process, and in cases where a high level of
humidity is anticipated, the use of conformal coatings after
cleaning to keep out moisture.
2.11 Power Supply Considerations
As these devices use the power supply itself as an analog
reference, the power should be very clean and come from a
separate regulator. A standard inexpensive LDO type regulator
should be used that is not also used to power other loads such
as LEDs, relays, or other high current devices. Load shifts on
the output of the LDO can cause Vdd to fluctuate enough to
cause false detection or sensitivity shifts.
Ceramic 0.1uF bypass capacitors should be placed very close
and routed with short traces to all power pins of the IC. There
should be at least 3 such capacitors around the part.
2.12 Startup / Calibration Times
The devices require initialization times as follows:
1. From very first powerup to ability to communicate:
2,083ms (one time event to initialize all of eeprom, or to
recover eeprom copy from FLASH in the event of
eeprom corruption)
2. From powerup to ability to communicate:
2,100 ms in the event the part is being forced to restore
the factory defaults.
3. From powerup to ability to communicate:
36 ms in the event the setups have been changed and
the part needs to backup the EEPROM to flash.
4. Normal cold start to ability to communicate:
3ms (Normal initialization from any reset)
5. Calibration time per key vs. burst spacings for 32 and 48
enabled keys (Table below):
lQ
6 QT60486-AS R8.01/0105

6 Page









QT60326 pdf, datenblatt
SPI communications operates in slave mode only, and obeys
DRDY control signaling. The clocking is as follows:
Clock idle:
Clock shift out edge:
Clock data in edge:
Max clock rate:
High
Falling
Rising
4MHz
SPI mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for data
from the host (master). This pin should be connected to the
MOSI (DO) pin of the host device.
MISO - Master in / Slave out data pin; used as an output for
data to the host. This pin should be connected to the M ISO
(DI) pin of the host. MISO floats when /SS is high to allow
multi-drop communications along with other slave parts.
SCK - SPI clock - input only clock from host. The host must shift
out data on the falling SCK edge; the QT60xx6 clocks data in
on the rising edge. The QT60xx6 likewise shifts data out on
the falling edge of SCK back to the host so that the host can
shift the data in on the rising edge. Important: SCK must
idle high; it should never float.
/SS - Slave select - input only; acts as a framing signal to the
sensor from the host. /SS must be low before and during
reception of data from the host. It must not go high again
until the SCK line has returned high; /SS must idle high. This
pin includes an internal pull-up resistor of 20K ~ 50K. When
/SS is high, MISO floats.
DRDY - Data Ready - active-high - indicates to the host that the
QT is ready to send or receive data. This pin idles high. This
pin includes an internal pull-up resistor of 20K ~ 50K. In SPI
mode this pin is an output only (i.e. open drain with internal
pull-up).
The MISO pin on the QT floats in 3-state mode between bytes
when /SS is high. This facilitates multiple devices on one SPI
bus.
Null Bytes: When the QT responds to a command with one or
more response bytes, the host should issue a null commands
(0x00) to get the response bytes back. The host should not
send new commands until all the responses are accepted back
from the QT from the prior command via nulls.
New commands attempted during intermediate byte transfers
are ignored.
Wake operation: The device can be put into sleep mode with a
serial command, 0x16 (page 16) and then be awakened later
with a 10µs minimum low level on the WS pin. With the /SS line
tied to WS, the host can simply toggle /SS low for 10µs
minimum to wake the part; the host should not send an actual
SPI byte to prevent the device from seeing a byte it cannot
properly interpret due to timing errors during wakeup.
The recommended method to reestablish communications after
Wake from Sleep is to send the QT device a 0x0F ('Get Last
Command' command) repeatedly until the correct response
comes back (the command's own compliment, i.e. 0xF0).
SPI Line Noise: In some designs it is necessary to run SPI
lines over ribbon cable across a lengthy distance on a PCB.
This can introduce ringing, ground bounce, and other noise
problems which can introduce false SPI clocking or false data.
Simple RC networks and slower data rates are helpful to
resolve these issues as shown in Figure 3-2.
CRC checks have also been added to critical commands in
order to detect transmission errors to a high level of certainty.
3.3 UART Communications
See also SR setup parameter, page 23.
UART mode is selected as soon as the QT receives any data
on the UART Rx pin. There is no other configuration required to
make the device operate in UART mode. Once UART is
selected after a power-up, the device cannot switch to SPI
mode unless the device is reset.
UART mode communications functions in the same basic way
as SPI communications. The Baud rate is adjusted by means of
setup parameter ‘SR’ (page 23). Once a new Baud rate has
been set, the device must be reset for the new rate to take
effect.
The major difference with SPI mode is that the UART mode is
asynchronous and so the host does not clock the QT. No
framing /SS or clock signal is required, simplifying the interface
greatly. Return data is sent from the QT back to the host when
the data is ready.
Figure 3-3 SPI Slave-Only Mode Timing (Fosc = 16MHz)
S1: m125ns S2: [20ns
S3: m25ns
S4: [20ns
S5: [20µs
S6: m1µs
S7: m125ns
S8: m125ns S9: m250ns
DRDY
(from QT)
high via pullup-R
S1
S5
/SS
(from Host)
S3
CLK
(from Host)
MOSI
(Data from Host)
?
MISO
(Data from QT)
3-state
Data shifts in to QT on rising edge
76543210
S2 {Command byte}
Data shifts out of QT on falling edge
?7 6 5 4 3 2 1 0
S4
3-state
S6
S9
S7 S8
76543210
{optional 2nd command byte}
?7 6 5 4 3 2 1 0
lQ
12
76543210
{null byte or next command to get QT response}
?7 6 5 4 3 2 1 0
data response
QT60486-AS R8.01/0105

12 Page





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