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PDF QT300 Data sheet ( Hoja de datos )

Número de pieza QT300
Descripción CAPACITANCE TO DIGITAL CONVERTER
Fabricantes QUANTUM 
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No Preview Available ! QT300 Hoja de datos, Descripción, Manual

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LQ
QT300
CAPACITANCE TO DIGITAL CONVERTER
Capacitance to Digital Converter (CDC) IC
Direct-to-digital conversion, 16 bits
Log response: Wide dynamic range
Outputs raw data to a host device
Single wire UART interface
Master or Slave mode SPI interface
Programmable clock speed
Turns objects into intrinsic touch sensors
One external sample capacitor to control gain
Multiple QT300’s possible on one SPI bus
DRDY
SCK
SNS1
Vss
1
2
3
4
8 Vdd
7 SDO
6 REQ / 1W
5 SNS2
The QT300 charge-transfer (“QT’”) IC is a self-contained Capacitance-to-
Digital-Converter (CDC) capable of detecting femotofarad level changes in
capacitance. While designed primarily for instrumentation applications, it can be used
also for touch control applications where signal processing is best handled by a host
MCU.
Primary applications include fluid level sensors, distance sensors, transducer
‘amplifiers’ for pressure and humidity sensing functions, material detectors, and other
uses requiring quantified capacitance data.
APPLICATIONS
Fluid level sensors
Prox sensors
Moisture detection
Position sensing
Transducer driver
Material sensors
Unlike other Quantum products, the QT300 does not process its acquired data. Its only result is raw, unprocessed binary
data which can be transmitted to a host via either a bidirectional SPI interface or a simple polled single wire UART type
interface. This allows the designer to treat the device as a capacitance-to-digital-converter (CDC) for measurement
applications. It is ideal for situations where there are unique signal processing requirements.
The device requires only a single sampling capacitor to function. The value of this capacitor controls the gain of the sensor,
and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components
are required.
The device operates on demand, and can be synchronized to allow several QT300’s to operate near each other without
cross-interference.
LQ
AVAILABLE OPTIONS
TA
00C to +700C
-400C to +850C
SOIC
-
QT300-IS
8-PIN DIP
QT300-D
-
Copyright © 2002 QRG Ltd
QT300 R1.02/0204

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QT300 pdf
If SM is set for idle-low SCK: Data is shifted out
of the QT300 on the rising edge of SCK and should
be shifted into the host on the falling edge of SCK.
If SM is set for idle-high SCK: Data is shifted out
of the QT300 on the falling edge of SCK and
should be shifted into the host on the rising edge of
SCK.
The maximum clock speed is 40kHz, and the
timings should obey the parameters Tskh and Tskl
in Table 7-2.
/DRDY - Data Ready (Optional); active low output
only. This indicates to the host that the device is
ready to send data back to the host. During idle
times this pin floats and therefore must be
connected to a pullup resistor.
The DRDY line can be used as a Slave Select line
(SS). The host does not need this line to operate in
many cases. DRDY can be used to 'frame' byte
transmissions.
Between bytes /DRDY will go high for a period
determined by the MLS setup parameter; the
minimum period is 8.3µs.
A typical Master mode SPI sequence is:
Figure 4-1 UART and Trigger Pulse Signal.
1) Host pulses /REQ low for 30µs.
2) QT300 acquires a signal in response to /REQ.
3) QT300 pulls /DRDY low when ready to send data.
4) Host detects /DRDY low and prepares to receive
data.
5) QT300 clocks out first byte of data (MSB).
6) QT300 sets /DRDY high for a duration determined
by Setup parameter MLS.
7) QT300 pulls /DRDY low.
8) QT300 clocks out the low byte (LSB).
9) QT300 releases /DRDY to float high.
overrun. The default value is 148 (resulting in a 500µs gap).
The relationship is:
Tmls (in µs) = (10 + MLS x 4) / 1.2
Where MLS = 0..255 (from user setup MLS)
Master SPI mode requires at least 3 signals to operate:
/REQ - Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
/REQ must return high before the end of the burst. If
/REQ is still low at the end of the burst the part goes into
Setup mode. The minimum duration of /REQ is 30µs.
SDO - Serial Data Output; Idle low output-only. This is the
data output to the host during an SPI transfer. When not in
use, this pin floats. This pin should be connected to the
SDI input pin of the host device.
SCK - SPI clock; Idle high or idle low, output-only. The idle
state is determined in Setups by the serial mode (SM)
parameter.
4 Serial 1W UART Interface
The single wire ('1W') UART interface allows all
communications to take place over a single bidirectional line
with a 10K pullup resistor. The host device triggers the
QT300 to acquire by means of a pulse sent to the QT300
over the wire. The Baud rate is established by the width of
this pulse; the pulse width establishes the bit rate of the
UART transmission to follow. The QT300 then acquires, and
responds by sending two bytes of data back over the 1W line
with a delay between the bytes as determined by parameter
MLS.
1W operation permits a device to be controlled from a single
pin on a host controller, using either a hardware or software
UART. Several QT300’s can coexist on a single host pin,
provided there is some logic steering.
This mode is set via the cloning process using parameter SM
(see Section 6).
LQ
5
QT300 R1.02/0204

5 Page





QT300 arduino
10000
9000
8000
7000
6000
200nF
120nF
80nF
40nF
5000
4000
3000
2000
1000
0
0 10 20 30 40 50
Cx Load, pF
Figure 7-4 Typical Burst Length versus Cx & Cs;
VDD = 5.0 Volts
1000
900
800
700
600
500
400
300
200
100
0
0
22nF
10nF
4.7nF
10 20 30 40 50
Cx Load, pF
Figure 7-5 Typical Burst Length versus Cx & Cs;
VDD= 5.0 Volts
500
400
300
200
Cs
9nF
19nF
43nF
74nF
124nF
200nF
100
0
0
11 21
Cx Load, pF
34
48
Figure 7-6 Typical resolution vs Cx & Cs;
Vdd = 3.0 Volts
150
Cs
125 43nF
74nF
100 124nF
200nF
75
50
25
0
0
11 21 34
Cx Load, pF
48
Figure 7-7 Typical resolution vs Cx & Cs;
Vdd = 3.0 Volts
LQ
11
QT300 R1.02/0204

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