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ADF4108 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4108
Beschreibung PLL Frequency Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 21 Seiten
ADF4108 Datasheet, Funktion
Data Sheet
PLL Frequency Synthesizer
ADF4108
FEATURES
GENERAL DESCRIPTION
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3.3 V systems
Programmable, dual-modulus prescaler
8/9, 16/17, 32/33, or 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
4 mm × 4 mm, 20-lead chip scale package
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(13-bit) counters, in conjunction with the dual-modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R counter), allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER
22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH-Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4108
Figure 1.
Rev. E
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ADF4108 Datasheet, Funktion
Data Sheet
ADF4108
TIMING CHARACTERISTICS
AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
Limit2 (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Guaranteed by design but not production tested.
2 Operating temperature range (B Version) is −40°C to +85°C.
t3 t4
CLOCK
DATA DB23 (MSB)
t1 t2
DB22
LE
LE
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Figure 2. Timing Diagram
Rev. E | Page 5 of 20

6 Page









ADF4108 pdf, datenblatt
Data Sheet
LATCH SUMMARY
REFERENCE COUNTER LATCH
ADF4108
RESERVED
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
N COUNTER LATCH
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)
FUNCTION LATCH
PRESCALER
VALUE
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
INITIALIZATION LATCH
PRESCALER
VALUE
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)
Figure 15. Latch Summary
Rev. E | Page 11 of 20

12 Page





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