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| Número de pieza | AN-6003 | |
| Descripción | Shoot-through | |
| Fabricantes | Fairchild Semiconductor | |
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AN-6003
“Shoot-through” in Synchronous Buck
Converters
Jon Klein
Power Management Applications
Abstract
The synchronous buck circuit is in widespread use to
provide “point of use” high current, low voltage
power for CPU’s, chipsets, peripherals etc. In the
synchronous buck converter, the power stage has a
“high-side” (Q1 below) MOSFET to charge the
inductor, and a “Low-side” MOSFET which replaces
a conventional buck regulator’s “catch diode” to
provide a low-loss recirculation path for the inductor
current.
V IN
H ig h -S id e
Q1
L1
VOUT
+
–
L o w -S id e
Q2
Figure 1. Synchronous Buck output stage
Shoot-through is defined as the condition when both
MOSFETs are either fully or partially turned on,
providing a path for current to “shoot through” from
VIN to GND. To minimize shoot-through,
synchronous buck regulator IC’s employ one of two
techniques to ensure “break before make” operation
of Q1 and Q2 to minimize shoot-through:
1. Fixed “dead-time”: A MOSFET is turned off,
then a fixed delay is provided before the low-
side is turned on. This circuit is simple and
usually effective, but suffers from its lack of
flexibility if a wide range of MOSFET gate
capacitances are to be used with a given
controller. Too long a dead-time means high
conduction losses. Too short a dead time can
cause shoot-through. A fixed dead-time
typically must err on the “too long” side to allow
high CGS MOSFETs to fully discharge before
turning on the complementary MOSFET.
2. Adaptive gate drive: This circuit looks at the
VGS of the MOSFET that’s being driven off to
determine when to turn on the complementary
MOSFET. Theoretically, adaptive gate drives
produce the shortest possible dead-time for a
given MOSFET without producing shoot-
through.
In practice, a combination of adaptive and fixed
produces the best results, and is typically what is in
today’s PWM controllers and gate drivers as shown
in Figure 2
BOOT RG
D1
+5
C BOOT
VIN
D
PWM
Delay
1V +
HDRV
SW
CGD
RGATE
G
CGS
S
Q1
D
PWM
Delay
LDRV
PGND
CGD
RGATE
G
CGS
S
Q2
1V
Figure 2. Typical Adaptive Gate drive
Even though there apparently is a “break before
make” action by the controller, shoot-through can
still occur when the High-side MOSFET turns on,
due to Gate Step.
Shoot-through is very difficult to measure directly.
Shoot-through currents persist for only a few nS,
hence the added inductance in a current probe
drastically affects the shoot-through waveform.
Shoot-through manifests itself typically as increased
ringing, reduced efficiency, higher MOSFET
temperatures (especially in Q1) and higher EMI.
This paper will provide analytical techniques to
predict shoot-through, and methods to reduce it.
04/25/2003
1 page  
Shoot-through in Synchronous Buck Regulators
AN-6003
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
MOSFET4
MOSFET1
MOSFET3
MOSFET5
MOSFET2
5 10 15 20 25 30 35
19V RiseTime(nS)
Figure 8 . Effect of SW node rise-time on V
STEP
VIN=19V, SW rise starts @ V = 0.5V
GS(Q2)
Table 4 shows the power loss due to shoot-through
for each MOSFET.
The major component of switching loss during Q1
turn-on is:
PTURN−ON
≈
tR
• FSW
•
VIN
• IOUT
2
(3)
and is computed in the right-most column for each
rise-time in Table 4 for IOUT = 15A.
TR(SW) FET1 FET2 FET3 FET4 FET5 Q1 tR Loss
5 18 10 10 56 27
214
10 12 6
6 39 24
428
15 7 3 3 28 19 641
20 3 0 0 19 16 855
25 0 0 0 11 12 1,069
30 0 0 0 4 8 1,283
Table 4. Worst case (Min V ) shoot-through
TH
power loss (mW)
SW rise starts @ V = 0.5V
GS(Q2)
In most cases, the shoot-through is negligble, so
slowing down high-side rise-time would not be a
prudent choice, since the more power would be lost
in slowing down the rise time than power saved by
eliminating shoot-through.
If, the controller's gate drive starts to turn Q1 on
before allowing the internal node of Q2 to discharge,
SW will rise when there is still a substantial VGS on
Q2 as shown is Table 5. Slowing down Q1 can then
be an effective strategy to reduce shoot-through
losses.
TR(SW)
5
10
15
20
25
30
FET1
90
30
23
16
8
0
FET2
62
31
26
21
16
11
FET3
29
24
18
13
7
1
FET4
380
127
61
50
39
25
FET5
551
266
58
54
51
47
Q1 tR Loss
214
428
641
855
1,069
1,283
Table 5. Worst case (Min VTH) shoot-through
power loss (mW)
SW rise starts @ VGS(Q2) = 1V
This is typically achieved by adding resistance (RG
in Figure 2) in series with CBOOT . An approximation
for TR provides a good starting point for choosing a
value of RG:
( )TR ≈ CGS • RDRIVE(L −H) + RG
(4)
where RDRIVE(L-H) is the resistance of the IC’s high-side
MOSFET gate driver when driving from low to high.
04/25/2003
5
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