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UJA1065 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UJA1065
Beschreibung High-speed CAN/LIN fail-safe system basis chip
Hersteller NXP Semiconductors
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Gesamt 30 Seiten
UJA1065 Datasheet, Funktion
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Rev. 07 — 25 February 2010
Product data sheet
1. General description
The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete components that
are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN)
and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all
networking applications that control various power and sensor peripherals by using
high-speed CAN as the main network interface and LIN as a local sub-bus. The fail-safe
SBC contains the following integrated devices:
High-speed CAN transceiver, interoperable and downward compatible with CAN
transceivers TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
Advanced independent watchdog
Dedicated voltage regulators for microcontroller and CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and subsystem levels
The UJA1065 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide full monitoring and a
software-driven fall-back operation.
The UJA1065 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.






UJA1065 Datasheet, Funktion
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Table 2. Pin description …continued
Symbol Pin Description
INH/LIMP 17 inhibit/limp-home output (BAT14 related, push-pull, default floating)
WAKE
18 local wake-up input (BAT42 related, continuous or cyclic sampling)
n.c. 19 not connected
V2 20 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin
CANH
21 CANH bus line (HIGH in dominant state)
CANL
22 CANL bus line (LOW in dominant state)
GND
23 ground
SPLIT
24 CAN-bus common mode stabilization output
LIN 25 LIN-bus line (LOW in dominant state)
RTLIN
26 LIN-bus termination resistor connection
BAT14
27 14 V battery supply input
n.c. 28 not connected
SYSINH 29 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC
converter)
V3 30 unregulated 42 V output (BAT42 related; continuous output, or Cyclic mode
synchronized with local wake-up input)
SENSE 31 fast battery interrupt / chatter detector input
BAT42
32 42 V battery supply input (connect this pin to BAT14 in 14 V applications)
The exposed die pad at the bottom of the package allows better dissipation of heat from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND for the best EMC
performance.
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
6 of 76

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UJA1065 pdf, datenblatt
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
6.2.7 Flash mode
Flash mode can only be entered from Normal mode by entering a specific Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the
SBC will enter Start-up mode and perform a system reset with the related reset source
information (bits RSS[3:0] = 0110).
From Start-up mode the application software now has to enter Flash mode within tWD(init)
by writing Operating Mode code 011 to the Mode register. This feeds back a successfully
received hardware reset (handshake between the SBC and the microcontroller). The
transition from Start-up mode to Flash mode is possible only once after completing the
Flash entry sequence.
The application can also decide not to enter Flash mode but to return to Normal mode by
using the Operating Mode code 101 for handshaking. This erases the Flash mode entry
sequence.
The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,
but Operating Mode code 111 must be used for serving the watchdog. If this code is not
used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up
mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash
mode), which results in a system reset with the corresponding reset source information.
Other Mode register codes will cause a forced reset with reset source code ‘illegal Mode
register code’.
6.3 On-chip oscillator
The on-chip oscillator provides the clock signal for all digital functions and is the timing
reference for the on-chip watchdog and the internal timers.
If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is
an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the
oscillator has recovered to its normal frequency and the system receives a wake-up
event.
6.4 Watchdog
The watchdog provides the following timing functions:
Start-up mode; needed to give the software the opportunity to initialize the system
Window mode; detects too early and too late accesses in Normal mode
Time-out mode; detects a too late access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
Off mode; fail-safe shut-down during operation thus preventing any blind spots in the
system supervision
The watchdog is clocked directly by the on-chip oscillator.
To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are
coded with redundant bits. Therefore, only certain codes are allowed for a proper
watchdog service.
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
12 of 76

12 Page





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