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PDF MAX7367 Data sheet ( Hoja de datos )
| Número de pieza | MAX7367 | |
| Descripción | (MAX7367 - MAX7369) 4-Channel I2C Switches / Multiplexer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0644; Rev 0; 10/06
4-Channel I2C Switches/Multiplexer
General Description
The MAX7367/MAX7368/MAX7369 bidirectional, four-
channel I2C switches/multiplexer expand the main I2C
bus up to four extended buses. The MAX7369 1:4
multiplexer connects the main I2C bus to one channel
at a time. The MAX7367/MAX7368 four-channel
switches connect the main I2C bus to one or more
channels at a time.
These devices isolate bus loading by extending the I2C
bus onto different channels. The MAX7367/MAX7368/
MAX7369 allow more devices to be interconnected to a
master controller and multiple devices with the same
I2C address to communicate to a master. The channels
are selected through the main I2C bus by writing to the
internal control register of the device.
Any device connected to an I2C bus can transmit and
receive signals. The MAX7367/MAX7368/MAX7369 are
transparent to signals sent and received at each chan-
nel, allowing multiple masters. These devices are com-
patible with the I2C protocol of clock stretch,
synchronization, and arbitration in case multiple mas-
ters address the bus at the same time.
All devices are set to the default state during initial
power-up. The MAX7367/MAX7368 have a RESET input
allowing external circuitry to set the MAX7367/MAX7368
to its default state anytime after the device has pow-
ered up. The MAX7367/MAX7369 have interrupt inputs,
allowing devices on the extended bus to send an inter-
rupt signal to the master on the main bus.
The MAX7367/MAX7369 are available in 20-pin TSSOP
packages, and the MAX7368 is available in a 16-pin
TSSOP package. All devices operate over the -40°C to
+85°C extended temperature range.
Servers
RAID
Cellular Phones
Base Stations
PCs
Multimedia Electronics
SAN/NAS
Applications
Features
♦ Four-Channel, Bidirectional Bus Expansion
♦ Voltage-Level Translation
♦ Low 6µA (typ) Supply Current, 0.1µA (typ)
Standby Current
♦ Low 16Ω (typ) On-Resistance
♦ Channel Selection Through I2C
♦ I2C-Compatible Normal or Fast Mode
♦ Device Address Selection
Up to Four Addresses (MAX7367)
Up to Eight Addresses (MAX7368/MAX7369)
♦ Bus-Loading Isolation
♦ Support Clock Stretch, Synchronization, and
Arbitration
♦ Hot Insertion
♦ 2.3V to 5.5V Supply Voltage Range
♦ 5V-Tolerant Inputs
♦ Interrupt from Extended Buses
(MAX7367/MAX7369)
♦ Hardware Reset (MAX7367/MAX7368)
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX7367EUP+* -40°C to +85°C 20 TSSOP
MAX7368EUE+* -40°C to +85°C 16 TSSOP
MAX7369EUP+ -40°C to +85°C 20 TSSOP
+Denotes lead-free package.
*Future product—contact factory for availability.
PKG
CODE
U20-3
U16-1
U20-3
Pin Configurations
TOP VIEW
+
A0 1
A1 2
RESET 3
INT0 4 MAX7367
SD0 5
SC0 6
INT1 7
SD1 8
SC1 9
GND 10
20 VDD
19 SDA
18 SCL
17 INT
16 SC3
15 SD3
14 INT3
13 SC2
12 SD2
11 INT2
TSSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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4-Channel I2C Switches/Multiplexer
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
Fall Time of Both SDA and SCL
Signals
SYMBOL
tf
CONDITIONS
fSCL = 100kHz
fSCL = 400kHz (Note 4)
Capacitive Load for Each Bus Line
Pulse Width of Spikes Suppressed
Data Valid Time from High to Low
Data Valid Time from Low to High
Data Valid Acknowledge
INT (Figure 2)
INT_ to INT Active Valid Time
INT_ to INT Inactive Delay Time
Low-Level, Pulse-Width Rejection
or INT_ Inputs
Cb
tSP
tVD;DATL
tVD;DATH
tVD;ACK
(Note 5)
(Note 6)
(Note 6)
tIV
tIR
tW(REJ)L
MIN TYP MAX
300
20 +
0.1Cb
300
400
50
1
0.6
1
UNIT
ns
pF
ns
µs
µs
µs
4 µs
2 µs
1 µs
High-Level, Pulse-Width Rejection
or INT_ Inputs
tW(REJ)H
0.5 µs
RESET (Figure 3)
Pulse-Width Low Reset
Reset Time (SDA Clear)
tWL(RST)
tRST
4
500
ns
ns
Recovery to Start
tREC;STA
0 ns
Note 1. All parameters are production tested at TA = +25°C and guaranteed by design over the specified temperature range.
Note 2. Pass gate propagation delay is calculated from 20Ω (typ) RON and the 15pF load capacitance. Not production tested.
Note 3. A master device must provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL) in order to
bridge the undefined region of SCL’s falling edge.
Note 4. Cb = total capacitance of one bus line in pF.
Note 5. Guaranteed by design.
Note 6. Measurements taken with a 1kΩ pullup resistor and 50pF load.
SDA
tf
SCL
S
tLOW
tHD;STA
tSU;DAT
tr tf
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSP tr
tBUF
tSU;STO
P
S
Figure 1. 2-Wire Serial-Interface Timing Diagram
_______________________________________________________________________________________ 5
5 Page 
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SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
VDD
SCL
SDA
INT[0–3]
4-Channel I2C Switches/Multiplexer
MAX7369 Functional Diagram
POWER-ON
RESET
SWITCH CONTROL LOGIC
MAX7369
GLITCH FILTER
I2C BUS
CONTROL
INTERRUPT LOGIC
A0
A1
A2
INT
GND
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX7367.PDF ] | |
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