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PDF SY55855V Data sheet ( Hoja de datos )
| Número de pieza | SY55855V | |
| Descripción | DUAL CML/PECL/LVPECL-to-LVDS TRANSLATOR | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY55855V (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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Micrel
DUAL CML/PECL/LVPECL-to-LVDS
TRANSLATOR
SuperLite™
SuperLSYit5e5™855V
SY55855V
FINAL
FEATURES
s Guaranteed fMAX >750MHz over temperature
s 1.5Gbps throughput capability
s 3.0V to 5.7V power supply
s Guaranteed <700ps propagation delay over
temperature
s Guaranteed <50ps within-device skew over
temperature
s LVDS compatible outputs
s Fully differential I/O architecture
s Wide operating temperature range: –40°C to +85°C
s Available in a tiny 10-pin MSOP package
PIN CONFIGURATION
D0 1
/D0 2
D1 3
/D1 4
GND 5
10 VCC
9 Q0
8 /Q0
7 Q1
6 /Q1
10-Pin MSOP
SuperLite™
DESCRIPTION
The SY55855V is a fully differential, CML/PECL/
LVPECL-to-LVDS translator. It achieves LVDS signaling
up to 1.5Gbps, depending on the distance and the
characteristics of the media and noise coupling sources.
LVDS is intended to drive 50Ω impedance transmission
line media such as PCB traces, backplanes, or cables.
SY55855V inputs can be terminated with a single
resistor between the true and the complement pins of a
given input.
The SY55855V is a member of Micrel’s new
SuperLite™ family of high-speed logic devices. This family
features very small packaging, high signal integrity, and
operation at many different supply voltages.
APPLICATIONS
s High-speed logic
s Data communications systems
s Wireless communications systems
s Telecom systems
FUNCTIONAL BLOCK DIAGRAM
D0 Q0
/D0 /Q0
D1 Q1
/D1 /Q1
PIN NAMES
Pin
D0, /D0
D1, /D1
Q0, /Q0
Q1, /Q1
GND
VCC
Function
CML/PECL/LVPECL Input Data
CML/PECL/LVPECL Input Data
LVDS Output Data
LVDS Output Data
Ground
VCC
SuperLite is a trademark of Micrel, Inc.
1
Rev.: C Amendment: /0
Issue Date: March 2003
1 page  
Micrel
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 3.0V to 5.7V; GND = 0V; TA = –40°C to +85°C(2)
Symbol
Parameter
Min.
Typ.
Max.
Unit
fMAX
tPLH
tPHL
tSKEW
Maximum Operating Frequency
Propagation Delay
D0 to Q0, D1 to Q1
Within-Device Skew(3)
Part-to-Part Skew (Diff.)
750 —
— MHz
300 — 700 ps
— — 50 ps
— — 250
tr
tf
Note 1.
Note 2.
Note 3.
LVDS Output Differential
Rise/Fall Times (20% to 80%)
100 — 300 ps
Specification for packaged product only.
Equilibrium temperature.
Worst case difference between Q0 and Q1 from either D0 or D1, when both outputs have the same transition.
SuperLite™
SY55855V
Condition
PRODUCT ORDERING CODE
Ordering
Code
SY55855VKI
Package
Type
K10-1
Operating
Range
Industrial
Package
Marking
855V
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SY55855V.PDF ] | |
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