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79RC32364 Schematic ( PDF Datasheet ) - IDT

Teilenummer 79RC32364
Beschreibung RISController Embedded 32-bit Microprocessor
Hersteller IDT
Logo IDT Logo 




Gesamt 21 Seiten
79RC32364 Datasheet, Funktion
www.DataSheet4U.com
RISControllerTM Embedded 32-bit
Microprocessor, based on
RISCore32300
79RC32364
Features
x High-performance embedded RISControllerTM
microprocessor, based on IDT RISCore32300TM 32-bit CPU
core
– Based on MIPS 32 RISC architecture with enhancements
– Scalar 5-stage pipeline minimizes branch and load delays
– 66 Million multiply accumulate (MAC) Mul-Add/second
@ 133MHz
– 100 and 133 frequencies
x MIPS 32 (ISA) instruction set architecture
– MIPS IV compatible conditional move instructions
– MIPS IV superset PREF (prefetch) instruction
– Fast multiplier with atomic multiply-add, multiply-sub
– Count leading zeros/ones instructions
x Large, efficient on-chip caches
– Separate 8kB Instruction cache and 2kB Data cache
– 2-way set associative
– Write-back and write-through support on a per page basis
– Optional cache locking with “per line” resolution, to facilitate
deterministic response
– Simultaneous instruction and data fetch in each clock cycle,
sustained rate, achieves over 1 GB/sec bandwidth
x Flexible RC4000 compatible MMU with 32-page TLB on-chip
– Variable page size
– Variable number of locked entries
– No performance penalty for address translation
x Flexible bus interface allows simple, low-cost designs
– Bus interface runs at a fraction of pipeline rate
– Programmable port-width interface (8-,16-, 32-bit memory and
I/O regions)
– Programmable bus turnaround times (BTA)
– Supports single data or burst transactions
x Improved real-time support
– Fast interrupt decode
x Low-power operation
– Active power management: powers down inactive units
– Typical power 700mW @ 133MHz
– Stand-by mode <300mW
x Enhanced JTAG interface, for low-cost in-circuit emulation
(ICE)
x MIPS architecture ensures applications software
compatibility throughout the RISController series of
embedded processors
x Industrial temperature range support
x 3.3V operation (core and I/O)
Block Diagram
RISCore32300TM
Extended MIPS 32
Integer CPU Core
MMU RISCore4000 Compatible
w/ System Control
TLB Coprocessor (CPO)
8kB I-Cache,
2-set, lockable
2kB D-Cache, 2-set,
lockable, write-back/write-through
Clock
Generation
Unit
RISCore32300 Internal Bus Interface
RC32364 Bus Interface Unit
The IDT logo is a registered trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
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*Notice: The information in this document is subject to change without notice
June 20, 2000
DSC 4510






79RC32364 Datasheet, Funktion
79RC32364™
RC32364
Clock
Serial
PIO
RC32134
CPU I/F
Timers,
UART,
Interrupt Ctl
DMA
Channels
DRAM Ctl
Memory &
I/O Ctl
Address &
Control
PCI Bridge with Arbiter
32-bit, 33Mhz PCI Bus
32-bit Data
Bus
SDRAM
Memory
& I/O
Figure 1 System Block Diagram
Pin Description Table
The following is a list of the system interface pins available on the RC32364. Pin names ending with an asterisk (*) are active when low.
Pin Type
Description
System Interface
AD(31:4) I/O Addr(31:4)/Data(31:4)
High-order multiplexed address and data bits. Regardless of system byte ordering, AD(31) is the MSB of the address.
AD(3:0)
I/O Size(3:0)/Data(3:0)
Valid sizes for the RC32364 are as follows:
Addr(3:2)
O
ALE
ADS*
O
O
Size(3) Size(2) Size(1)
00
00
00
00
01
0
0
1
1
0
Size(0)
0
1
0
1
0
Transfer
Width
16 bytes
1 byte
2 bytes
3 bytes
4 bytes
Other encodings allow future generations to service other transfer sizes. During the data phase, AD[3:0] represents the Data(3:0).
Addr(3:2)
Non-multiplexed address lines. These serve as the word within block address for cache refills (Addr(3:2)). The word within block
address bits count in a sub-block ordering.
Address Latch Enable.
This signal provides set-up and hold times around the address phase of the AD bus.
Address Strobe
This active-low signal indicates valid address and the start of a new bus transaction. The processor asserts ADS* for the entire
address cycle. This is the inverse of the ALE signal.
Table 3 System Interface Pin Descriptions (Page 1 of 4)
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79RC32364 pdf, datenblatt
79RC32364™
Absolute Maximum Ratings
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol
Rating
RC32364
3.3V±5%
RC32364
3.3V±5%
Unit
Commercial Industrial
VTERM
Terminal Voltage with respect to GND –0.51 to 4.0
–0.51 to 4.0
V
TC
Operating Temperature(case)
0 to +85
-40 to +85
°C
TBIAS
Case Temperature Under Bias
–55 to +125
–55 to +125
°C
TSTG Storage Temperature
–55 to +125
–55 to +125
°C
IIN DC Input Current
202 202 mA
IOUT DC Output Current
503 503 mA
1.
2.
3.
VIN minimum = –2.0V for pulse width less than
When VIN < 0V or VIN > VCC
Not more than one output should be shorted at
15ns. VIN should not exceed
a time. Duration of the short
VCC +0.5 Volts.
should not exceed
30
seconds.
Recommended Operation Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +85°C (Case)
-40°C + 85°C (Case)
Gnd
0V
0V
RC32364
VCC Core & Vcc I/O
3.3V±5%
3.3V±5%
AC Electrical Characteristics — Commercial/Industrial Temperature
Ranges—RC32364
VCC Core & VCC I/O = 3.3V ± 5%; TCase = 0°C to +85°C Commercial, TCase = -40° C to +85°C Industrial
Clock Parameters—RC32364
Note: Operation of the RC32364 is only guaranteed with the Phase Lock Loop enabled
Parameter
Symbol
Test
Conditions
Pipeline clock frequency
PClk
MasterClock HIGH
tMCHIGH
Transition 2ns
MasterClock LOW
tMCLOW
Transition 2ns
MasterClock Frequency
MasterClock Period
Clock Jitter for MasterClock1
MasterClock Rise Time2
MasterClock Fall Time2
tMCP
tJitterIn1
tMCRise
tMCFall
JTAG Clock Period
tTCK
JTAG Clock High and Low Time tTCKLOW, tTCKHIGH
JTAG Clock Fall and Rise Time tTCKFall, tTCKRise
1. Guaranteed by design
2. Rise and Fall times are measured between 10% and 90%.
RC32364 100MHz
Min Max
80 100
6—
6—
10 50
20 100
±250
—3
—3
100 —
40 —
—3
RC32364 133MHz
Min Max
80 133
5—
5—
10 67
15 100
±250
—3
—3
100 —
40 —
—3
Units
MHz
ns
ns
MHz
ns
ps
ns
ns
ns
ns
ns
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