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PDF ATAR080 Data sheet ( Hoja de datos )
| Número de pieza | ATAR080 | |
| Descripción | Low-current Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features/Benefits
• Very Low Power Consumption in Active, Power-down and Sleep Mode
• 2-Kbyte ROM, 256 × 4-bit RAM
• 12 Bi-directional I/Os
• Up to 6 External/Internal Interrupt Sources
• Multifunction Timer/Counter
• Programmable System-clock with Prescaler and Five Different Clock Sources
• Wide Supply-voltage Range (1.8 V to 6.5 V)
• Very Low Sleep Current (< 1 µA)
• Synchronous Serial Interface (2-wire, 3-wire)
• Watchdog, POR and Brown-out Function
• Voltage Monitoring Inclusive Lo_BAT Detection
• Flash Controller ATAM893 available (SSO20)
Description
The ATAR080 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervision, interval timer with watch-
dog function and a sophisticated on-chip clock generation with external clock input,
integrated RC-, 32-kHz and 4-MHz crystal-oscillators.
Figure 1. Block Diagram
VSS VDD
NRST/
OSC1 OSC2
Low-current
Microcontroller
for Wireless
Communication
ATAR080
BP20/NTE
BP21
BP22
BP23
Brown-out
protect RESET
Voltage Monitor
External input
VMI
RC Crystal External
oscillators oscillators clock input
Clock management
ROM
RAM
2 K × 8 bit 256 × 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
BP40 BP42
INT3 T2O
SC
BP41 BP43
VMI INT3
T2I SD
BP50 BP52
INT6 INT1
BP51 BP53
INT6 INT1
Rev. 4675D–4BMCU–12/04
1 page  
Registers
Program Counter (PC)
4675D–4BMCU–12/04
ATAR080
Figure 5. RAM Map
RAM
(256 × 4-bit)
Autosleep
FCh
X
Y
SP TOS-1
RP
04h
00h
Expression Stack
30
FFh
Global
variables
TOS
TOS-1
TOS-2
SP
4-bit
Expression
stack
Return
stack
07h
Global
variables
03h
Return Stack
11 0
12-bit
RP
The microcontroller has seven programmable registers and one condition code register
(see Figure 6).
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches), the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the table instruction
to fetch 8-bit wide ROM constants.
Figure 6. Programming Model
11
PC
0
7
RP
0
00
7
SP
0
7
X
0
7
Y
0
3
TOS
0
30
CCR C -- B I
Program Counter
Return Stack Pointer
Expression Stack Pointer
RAM Address Register (X)
RAM Address Register (Y)
Top of Stack Register
Condition Code Register
Interrupt enable
Branch
Reserved
Carry/borrow
5
5 Page 
ATAR080
Watchdog Reset
External Clock Supervisor
Voltage Monitor
Figure 10. Brown-out Detection
VDD
1.95 V
1.65 V
CPU
Reset
BOT = 1
CPU
Reset BOT = 0
td
td
td = 1.5 ms (typically)
t
td
Note: BOT = 1, low brown-out voltage threshold. (1.65 V is the reset value).
BOT = 0, high brown-out voltage threshold (1.95 V).
A power-on reset pulse is generated by a VDD rise across the default BOT voltage level
(1.65 V). A brown-out reset pulse is generated when VDD falls below the brown-out volt-
age threshold. Two values for the brown-out voltage threshold are programmable via
the BOT bit in the SC register. When the controller runs in the upper supply voltage
range with a high system clock frequency, the high threshold must be used. When it
runs with a lower system clock frequency, the low threshold and a wider supply voltage
range may be chosen. For further details, see the electrical specification and the SC
register description for BOT programming.
The watchdog's function can be enabled at the WDC-register and triggers a reset with
every watchdog counter overflow. To suppress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog register address (CWD). The
CPU reacts in exactly the same manner as a reset stimulus from any of the above
sources.
The external input clock supervisor function can be enabled if the external input clock is
selected within the CM- and SC registers of the clock module. The CPU reacts in exactly
the same manner as a reset stimulus from any of the above sources.
The voltage monitor consists of a comparator with internal voltage reference. It is used
to supervise the supply voltage or an external voltage at the VMI pin. The comparator for
the supply voltage has three internal programmable thresholds: one lower threshold
(2.15 V), one middle threshold (2.55 V) and one higher threshold (2.95 V). For external
voltages at the VMI pin, the comparator threshold is set to VBG = 1.25 V. The VMS-bit
indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this thresh-
old. An interrupt can be generated when the VMS-bit is set or reset to detect a rising or
falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit
(VIM) is reset in the VMC-register.
4675D–4BMCU–12/04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATAR080.PDF ] | |
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