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PDF IRF7324D1 Data sheet ( Hoja de datos )

Número de pieza IRF7324D1
Descripción FETKY MOSFET / Schottky Diode
Fabricantes International Rectifier 
Logotipo International Rectifier Logotipo



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PD- 91789
PRELIMINARY
IRF7324D1
FETKYMOSFET / Schottky Diode
l Co-packaged HEXFET® Power
MOSFET and Schottky Diode
l Ideal for Mobile Phone Applications
l Generation V Technology
l SO-8 Footprint
A1
A2
S3
G4
8K
7K
6D
5D
Description
Top View
The FETKYTM family of co-packaged HEXFETs and Schottky diodes offer
the designer an innovative board space saving solution for switching
regulator applications. Generation 5 HEXFETs utilize advanced processing
techniques to achieve extremely low on-resistance per silicon area. Combining
this technology with International Rectifier's low forward drop Schottky
rectifiers results in an extremely efficient device suitable for use in a wide
variety of portable electronics applications.
VDSS = -20V
RDS(on) = 0.18
Schottky Vf = 0.39V
The SO-8 has been modified through a customized leadframe for enhanced
thermal characteristics. The SO-8 package is designed for vapor phase,
infrared or wave soldering techniques.
S O -8
Absolute Maximum Ratings (TA = 25°C unless otherwise noted)
Parameter
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
PD @TA = 70°C
Continuous Drain Current, VGS@4.5V
Pulsed Drain Current Œ
Power Dissipation 
Linear Derating Factor
Maximum
-2.9
-2.3
-23
2.0
1.3
16
VGS
dv/dt
Gate-to-Source Voltage
Peak Diode Recovery dv/dt 
± 12
-5.0
TJ, TSTG
Junction and Storage Temperature Range
-55 to +150
Thermal Resistance Ratings
Parameter
RθJA
Junction-to-Ambient 
Maximum
62.5
Notes:
ΠRepetitive rating; pulse width limited by maximum junction temperature (see figure 11)
 ISD -2.2A, di/dt -50A/µs, VDD V(BR)DSS, TJ 150°C
Ž Pulse width 300µs; duty cycle 2%
 Surface mounted on FR-4 board, t 10sec.
www.irf.com
Units
A
W
mW/°C
V
V/ns
°C
Units
°C/W
1

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IRF7324D1 pdf
IRF7324D1
Power Mosfet Characteristics
1500
1000
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SH O R TE D
C rss = C gd
C oss = Cds + C gd
C is s
Coss
10
I D = -2.2A
VDS = -16V
8
6
Crss
500
0A
1 10 100
-VDS , Drain-to-Source Voltage (V)
4
2
FOR TEST CIRCUIT
SEE FIGURE 12
0A
0 5 10 15 20 25
Q G , Total Gate Charge (nC)
Fig 9. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 10. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
D = 0.50
0.20
10
0.10
0.05
0.02
1 0.01
0.1
0.0001
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t1 / t 2
2. Peak TJ = P DM x ZthJA + TA
0.001
0.01 0.1
1
t1 , Rectangular Pulse Duration (sec)
10
100
Fig 9. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
www.irf.com
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