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PDF AT75C Data sheet ( Hoja de datos )
| Número de pieza | AT75C | |
| Descripción | Smart Internet Appliance Processor | |
| Fabricantes | ATMEL Corporation | |
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Features
• Fully Autonomous DSP System
• 16-bit Fixed-point OakDSPCore®
• 24K x 16 of Uploadable Program RAM
• 16K x 16 of Data RAM
• 2K x 16 of X-RAM
• 2K x 16 of Y-RAM
• X-RAM and Y-RAM Accessible within the Same Cycle
• JTAG Interface Available on AT75C220 and AT75C320
• On-chip Emulation Module
• Flexible Codec Interface
• Communication with External Processor through Dual-port Mailbox
Description
The AT75C DSP subsystem is an autonomous DSP-based computation block that co-
exists on-chip with other processors and functions. It is built around a 16-bit, fixed-
point, industry-standard OakDSPCore. Additionally, the DSP subsystem embeds all
elements necessary to run complex DSP algorithms independently without any exter-
nal resources.
The self-contained subsystem contains the OakDSPCore itself, program memory,
data memory, an on-chip emulation module and a flexible codec interface. These
resources allow the subsystem to run complex DSP routines, such as V.34 modem
emulation or state-of-the-art voice compression.
The codec interface permits connection of any external industry-standard codec
device, allowing the DSP subsystem to handle directly external analog signals such as
telephone line or handset signals.
Communication between the DSP subsystem and the on-chip ARM7TDMI™ core is
achieved through a semaphore-operated dual-port mailbox.
Smart Internet
Appliance
Processor
(SIAP™)
AT75C
DSP Subsystem
Rev. 1368C–INTAP–08/02
1
1 page  
Bus Architecture
Data Buses
Address Buses
AT75C DSP Subsystem
Data is transferred via the X-data bus (XDB) and the program data bus (PDB), 16-bit bi-
directional buses, and the Y-data bus (YDB), a 16-bit unidirectional bus. The XDB is the
main data bus, where most of the data transfers occur. Data transfer between the Y-
data memory (Y-RAM) and the multiplier (Y-register) occurs over the YDB when a multi-
ply instruction uses two data memory locations simultaneously. Instruction word fetches
take place in parallel over PDB.
The bus structure supports the following movements:
• Register to register
• Register to memory
• Memory to register
• Program to data
• Program to register
• Data to program
The bus structure can transfer up to two 16-bit words within one cycle.
Addresses are specified for the on-core X- and Y-RAM on the 16-bit unidirectional X-
address bus (XAB) and the 11-bit unidirectional Y-address bus (YAB). Program memory
addresses are specified on the 16-bit unidirectional program address bus (PAB).
1368C–INTAP–08/02
5
5 Page 
Normalization
Bit-field Operations
1368C–INTAP–08/02
AT75C DSP Subsystem
operand can be 36 bits when it is one of the accumulators or 16 bits when it is a data
memory location or one of the registers.
The algorithm for determining the exponent result for a 36-bit number is as follows: Let
N be the number of the sign bits (i.e., the number of MSBs equal to bit 36) found in the
evaluated number. This means that the exponent is evaluated with respect to bit 32. For
a 16-bit operand, the 16 bits are regarded as bits 16 31, sign-extended into bits 32 to 35
and then treated as a 36-bit operand. Therefore, in this case, the exponent result is
always greater than or equal to zero. For examples, refer to Table 1 on page 11.
A negative result represents a number for which the extension bits are not identical. The
value of this negative result stands for how many right shifts should be executed in order
to normalize the number, i.e., bit 31 (representing the sign) and bit 30 (representing part
of the magnitude) will be different. A positive result represents an un-normalized number
for which at least the four extension bits and the sign bits are the same. When evaluat-
ing the exponent value of one of the accumulators, the positive number is the amount of
left shifts that should be executed in order to normalize the source operand. An expo-
nent result equal to zero represents a normalized number.
Examples including an application in a normalization operation can be found in Table 1
below.
Table 1. Normalization Operation Examples
Evaluated Number
[35:...]
N Exponent Result N-5
0000 0000101...
8 3 (shift left by 3)
1100 10101...
2 -3 (shift right by 3)
0000 0111000...
5 0 (no shift)
Normalized Number
[35:...]
0000 0101...
1111...
0000 0111000...
Full normalization can be achieved in two cycles using the EXP instruction followed by a
shift instruction. For more details, refer to the section below on normalization, or to the
EXP, SHFC and MOVS instructions in “Instruction Set” on page 31.
The exponent unit can also be used in floating-point calculations, where it is useful to
transfer the exponent result into both the SV register and one of the Ax-accumulators.
Two techniques for normalization are provided. Using the first technique, normalization
can be done by two cycles using two instructions. The first instruction evaluates the
exponent value of one of the registers including the accumulators, or the value of a data
memory location. The second instruction is shifting the evaluated number according to
the exponent result stored at SV register. The second technique is using a normalization
step (NORM instruction). For details, refer to “Instruction Set” on page 31.
The bit-field operation unit (BFO) is used for set, reset, change or test a set of up to 16
bits within a data memory location or within one of the registers. The data memory loca-
tion can be addressed using a direct memory or an indirect address. The SET, RST and
CHNG instructions are read-modify-write and require two cycles and two words. The 16-
bit immediate mask value is embedded in the instruction opcode. Various testing
instructions can be used. Testing for zeros (TST0) or for ones (TST1), of up to 16 bits in
a single cycle, can be achieved when the mask is in one of the AxL or in two cycles
when the mask value is embedded in the instruction opcode.
Testing instruction (TSTB) for a specific bit, 1 out of 16, in a data memory location or in
one of the registers in a single cycle, is also available. For details, refer to SET, RST,
CHNG, TST0, TST1, TSTB instructions in the “Instruction Set” on page 31.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT75C.PDF ] | |
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