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WED2DL32512V Schematic ( PDF Datasheet ) - White Electronic

Teilenummer WED2DL32512V
Beschreibung 512Kx32 Synchronous Pipeline Burst SRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 9 Seiten
WED2DL32512V Datasheet, Funktion
www.DataSheet4U.com
WED2DL32512V
512Kx32 Synchronous Pipeline Burst SRAM PRELIMINARY*
FEATURES
s Fast clock speed: 200, 166, 150 & 133MHz
s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s Single +3.3V power supply (VDD)
s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
s Snooze Mode for reduced-power standby
s Single-cycle deselect
s Common data inputs and data outputs
s Individual Byte Write control and Global Write
s Clock-controlled and registered addresses, data I/Os and control signals
s Burst control (interleaved or linear burst)
s Packaging:
• 119-bump BGA package
s Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW0-3).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be from one to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
FIG. 1
PIN CONFIGURATION
(TOP VIEW)
123 4 5
A VDDQ SA
SA
NC
SA
B NC SA SA ADSC SA
C NC SA SA VDD SA
D DQc NC VSS NC VSS
E DQc DQc VSS CE VSS
F VDDQ DQc VSS OE VSS
G DQc DQc BWc NC BWb
H DQc DQc VSS NC VSS
J VDDQ VDD NC
VDD
NC
K DQd DQd VSS
CLK
VSS
L DQd DQd BWd NC BWa
M VDDQ DQd VSS BWE VSS
N DQd DQd VSS
SA1
VSS
P DQd NC VSS SA0 VSS
R NC SA MODE VDD NC
T NC NC SA SA SA
U VDDQ DC
DC
DC
DC
NOTE: DC = Do Not Connect
6
SA
SA
SA
NC
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
SA
NC
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
BLOCK DIAGRAM
512K x 16
SSRAM
DQa
DQb
512K x 16
SSRAM
DQc
DQd
BWc
BWd
January 2000 Rev. 0
1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com






WED2DL32512V Datasheet, Funktion
WED2DL32512V
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode In which the
device is deselected and current is reduced to ISB2Z. The duration of
SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs except ZZ become
gated inputs and are ignored. ZZ is an asynchronous, active HIGH
input that causes the device to enter SNOOZE MODE. When ZZ
becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is
met. Any READ or WRITE operation pending when the device enters
SNOOZE MODE is not guaranteed to complete successfully. There-
fore, SNOOZE MODE must not be initiated until valid pending
operations are completed.
SNOOZE MODE
Description
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
Conditions
ZZ VIH
Symbol
ISB2Z
tZZ
tRZZ
tZZI
tRZZI
Min
2(tKC)
Max
10
2(tKC)
2(tKC)
Units
mA
ns
ns
ns
ns
Notes
1
1
1
1
FIG. 2 SNOOZE MODE TIMING DIAGRAM
CLOCK
ZZ
ISUPPLY
ALL INPUTS
(except ZZ)
Output (Q)
tZZ
tZZI
IISB2Z
HIGH-Z
tRZZ
tRZZI
DESELECT or READ Only
DON'T CARE
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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