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PDF STP1N120 Data sheet ( Hoja de datos )

Número de pieza STP1N120
Descripción N-Channel Power MOSFET / Transistor
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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STP1N120
N-channel 1200V - 30- 500mA - TO-220
Zener - protected SuperMESH™ Power MOSFET
PRELIMINARY DATA
General features
Type
STP1N120
VDSS
1200V
RDS(on)
ID
< 38500mA
PW
45W
100% avalanche tested
Extremely high dv/dt capability
ESD improved capability
New high voltage benchmark
Gate charge minimized
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage Power MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
3
2
1
TO-220
Internal schematic diagram
Order codes
Part number
STP1N120
Marking
P1N120
Package
TO-220
Packaging
Tube
September 2006
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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STP1N120 pdf
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STP1N120
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Tbd
Min. Typ. Max. Unit
Tbd ns
Tbd ns
Tbd ns
Tbd ns
Table 7. Source drain diode
Symbol
Parameter
Test conditions
ISD
ISDM
Source-drain current
Source-drain current (pulsed)
VSD(1) Forward on voltage
ISD=1A, VGS=0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD=1A, VDD=100V
di/dt = 50A/µs,Tj=25°C
(see Figure 6)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD=1A,VDD=100V
di/dt=50A/µs,Tj=150°C
(see Figure 6)
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Min Typ. Max Unit
500 mA
2A
Tbd V
Tbd ns
Tbd nC
Tbd A
Tbd ns
Tbd nC
Tbd A
Table 8. Gate-source zener diode
Symbol
Parameter
Test conditions
Min Typ. Max Unit
BVGSO (1) Gate-source breakdown voltage Igs ± 1mA, (open drain) 30
V
1. The built-in-back zener diodes have specifically been designed to enhance not only the device’s ESD
capability, but also to make them safely absorb possibile voltage transients that may occasionally be
applied from gate to source. In this respect the zener voltage is appropriate to achieve an efficient and ost-
effective intervention to protect the device’s integrity. These integrated zener diodes thus avoid the usage
of external components.
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