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PDF MAX7470 Data sheet ( Hoja de datos )
| Número de pieza | MAX7470 | |
| Descripción | (MAX7469 / MAX7470) HDTV Continuously Variable Anti Aliasing Filters | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX7470 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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19-0548; Rev 0; 5/06
HDTV Continuously Variable
Anti-Aliasing Filters
General Description
The MAX7469/MAX7470 triple-channel, anti-aliasing fil-
ters and buffers are ideal for high-definition (HD) and
standard-definition (SD) television (TV) applications.
Compatible with 1080i, 720p, 720i, 480p, and 480i
scanning system standards and computer format sig-
nals, the MAX7469/MAX7470 support component video
(Y Pb Pr, GsBR, and RGBHV), as well as composite
(CVBS) and S-video (Y/C).
The MAX7469/MAX7470 limit the input bandwidth for
anti-aliasing and out-of-band noise reduction prior to
digital conversion by an ADC or video decoder. The
MAX7469/MAX7470 frequency response can be contin-
uously varied in 256 linear steps through an I2C* inter-
face from below SD resolution to beyond HD resolution.
The output buffers of the MAX7469/MAX7470 drive a
2VP-P video signal into a standard 150Ω load. The inputs
are AC-coupled, and the outputs can be either DC- or
AC-coupled. The MAX7469 has a gain of 0dB, and the
MAX7470 has a gain of +6dB. Both devices are available
in a 20-pin TQFN package and are fully specified over
the 0°C to +85°C upper-commercial temperature range.
Applications
HDTV (LCD, PDP, DLP, CRT)
Set-Top Boxes
Personal Video Recorders
Home Theaters
Pin Configuration
TOP VIEW
15 14 13 12 11
IN1 16
GND 17
IN2 18
GND 19
IN3 20
+
MAX7469
MAX7470
*EP
10 OUT1
9 AVDD
8 OUT2
7 AVDD
6 OUT3
1 2345
Features
♦ Continuously Variable Anti-Aliasing Filter
5MHz to 34MHz in 256 Steps
♦ Supports All Standard Video and Computer Input
Formats
480i, 480p, 720i, 720p, 1080i
QVGA, VGA, SVGA, XGA, SXGA, UXGA
Y Pb Pr, GsBR, RGBHV, Y/C, CVBS
♦ Accepts Any Input Sync Format
Sync on Y, Sync on G, External Sync (Positive
or Negative)
Sync on All Channels
♦ Buffered Outputs Drive Standard 150Ω Video
Load
0dB (MAX7469)
+6dB (MAX7470)
♦ DC- or AC-Coupled Outputs
♦ Single +5V Analog and +3.3V Digital Supplies
♦ 5mW Power-Down Mode
♦ 20-Pin TQFN Lead-Free Package
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associate Companies, conveys a
license under the Philips I2C Patent Rights to use these compo-
nents in an I2C system, provided that the system conforms to the
I2C Standard Specification defined by Philips.
Ordering Information
PART
PIN-PACKAGE
BUFFER
GAIN (dB)
PKG
CODE
MAX7469UTP+ 20 TQFN-EP*
0 T2055-4
MAX7470UTP+** 20 TQFN-EP*
+6 T2055-4
Note: All devices are specified over the 0°C to +85°C operating
temperature range.
+ Indicates lead-free packaging.
*EP = Exposed pad.
**Future product—contact factory for availability.
TQFN (5mm x 5mm)
*EXPOSED PAD.
SEE PIN DESCRIPTION FOR CONNECTION.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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HDTV Continuously Variable
Anti-Aliasing Filters
SDA
tf
SCL
tLOW tr tSU;DAT
tf
tHD;STA
tSP tr tSP
tHD;STA
S
tHD;DAT
tHIGH
Figure 1. 2-Wire, Serial-Interface Timing Diagram
tSU;STA
Sr
tSU;STO
P
S
Typical Operating Characteristics
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150Ω to GND, CLOAD = 0 to 20pF to GND, CIN = 0.1µF, TA = +25°C, unless otherwise noted.)
FREQUENCY RESPONSE (MAX7469)
10
0
-10
CODE 40
-20
-30
CODE 90
-40
CODE 220
CODE 255
-50
-60
-70
-80
0.1
1 10 100
FREQUENCY (MHz)
1000
PASSBAND FLATNESS (MAX7469)
1.0
0.5
0
-0.5 CODE 40
-1.0
CODE 90
-1.5
-2.0 CODE 220
-2.5 CODE 255
-3.0
0.1
1 10
FREQUENCY (MHz)
100
FREQUENCY RESPONSE (MAX7470)
10
0
-10
CODE 40
-20
CODE 220
-30 CODE 255
-40 CODE 90
-50
-60
-70
0.1
1 10 100
FREQUENCY (MHz)
1000
PASSBAND FLATNESS (MAX7470)
7.0
6.5
6.0
CODE 40
5.5
5.0 CODE 90
4.5
4.0 CODE 220
3.5 CODE 255
3.0
0.1
1 10
FREQUENCY (MHz)
100
90
80
70
60
50
40
30
20
10
0
0.1
GROUP DELAY
SD
HD
1 10
FREQUENCY (MHz)
100
2T RESPONSE (1 IRE = 7.14mV)
MAX7469 toc06
300mV/div
200ns/div
300mV/div
_______________________________________________________________________________________ 5
5 Page 
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HDTV Continuously Variable
Anti-Aliasing Filters
Acknowledge Bit (ACK) and Not-Acknowledge Bit
(NACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX7469/MAX7470
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period
of the clock pulse (Figure 4). To generate a NACK, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and leaves it high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccess-
ful data transfer happens if a receiving device is busy or
if a system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
The MAX7469/MAX7470 generate an acknowledge bit
when receiving an address or data by pulling SDA low
during the ninth clock pulse. When transmitting data
during a read, the MAX7469/MAX7470 do not drive
SDA during the ninth clock pulse (i.e., the external
pullups define the bus as a logic-high) so that the
receiver of the data can pull SDA low to acknowledge
receipt of data.
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition, followed by the 7-bit slave
address (Figure 5). When idle, the MAX7469/MAX7470
wait for a START condition, followed by their slave
address. The serial interface compares each address bit
by bit, allowing the interface to power down and discon-
nect from SCL immediately if an incorrect address is
detected. After recognizing a START condition followed
by the correct address, the MAX7469/MAX7470 are
ready to accept or send data. The least significant bit
(LSB) of the address byte (R/W) determines whether the
master is writing to or reading from the
MAX7469/MAX7470 (R/W = 0 selects a write condition,
R/W = 1 selects a read condition). After receiving the
proper address, the MAX7469/MAX7470 (slave) issue an
ACK by pulling SDA low for one clock cycle.
The MAX7469/MAX7470 slave address consists of 5
fixed bits, A6–A2 (set to 10010), followed by 2 pin-pro-
grammable bits, A1 and A0. The most significant
address bit (A6) is transmitted first, followed by the
remaining bits. Addresses A1 and A0 can also be driven
dynamically if required, but the values must be stable
when they are expected in the address sequence.
S
NOT ACKNOWLEDGE
SDA
SCL 1
Figure 4. Acknowledge and Not-Acknowledge Bits
ACKNOWLEDGE
89
.
SDA 1 0 0 1 0 A1 A0 R/W ACK
MSB
LSB
SCL
Figure 5. Slave-Address Byte Definition
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MAX7470.PDF ] | |
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