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PDF CY7C188 Data sheet ( Hoja de datos )
| Número de pieza | CY7C188 | |
| Descripción | 32K x 9 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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88
CY7C188
Features
• High speed
— 15 ns
• Automatic power-down when deselected
• Low active power
— 660 mW
• Low standby power
— 140 mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE
features
Functional Description
The CY7C188 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 9 bits. Easy memory expansion is
32K x 9 Static RAM
provided by an active-LOW chip enable (CE1), an active-HIGH
chip enable (CE2), an active-LOW output enable (OE), and
three-state drivers. The device has an automatic power-down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking CE1 and write
enable (WE) inputs LOW and CE2 input HIGH. Data on the
nine I/O pins (I/Oo – I/O8) is then written into the location spec-
ified on the address pins (A0 – A14).
Reading from the device is accomplished by taking CE1 and
OE LOW while forcing WE and CE2 HIGH. Under these con-
ditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The nine input/output pins (I/O0 – I/O8) are placed in a high-im-
pedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a
write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C188 is available in standard 300-mil-wide SOJs.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
CE1
CE2
WE
OE
INPUT BUFFER
32K x 9
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
Maximum Standby Current (mA)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
C188–1
Pin Configuration
DIP/SOJ
Top View
NC
NC
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A14
30 CE2
29 WE
28 A13
27 A9
26 A10
25 A11
24 OE
23 A12
22 CE1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
C188–2
7C188–15
15
120
35
7C188–20
20
170
35
7C188–25
25
165
35
7C188–35
35
160
30
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05053 Rev. **
Revised August 24, 2001
1 page  
Switching Waveforms (Continued)
ADDRESS
tWC
CE1
WE
tAW
tSA tPWE
tHA
OE
DATA I/O
NOTE 16
tHZOE
tSD
DATA IN VALID
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Timing parameters are the same for all chip enable signals (CE1 and CE2), so only the timing for CE1 is shown.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in the output state and input signals should not be applied.
Write Cycle No.2 (CE Controlled)[8,13,14,15]
ADDRESS
CE1
tWC
tSA
tAW
tSCE
tHD
tHA
WE
DATA I/O
Write Cycle No. 3 (WE Controlled, OE LOW)[9,13,15]
tSD
DATA IN VALID
tHD
CY7C188
C188–7
C188–8
Document #: 38-05053 Rev. **
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY7C188.PDF ] | |
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